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Top 144 vhdl open source projects

symbolator

HDL symbol generator

✭ 123

python vhdl verilog symbol hdl

mrisc32-a1

A pipelined, in-order, scalar VHDL implementation of the MRISC32 ISA

✭ 21

VHDL Makefile cpu vhdl risc soft-core fpu mrisc32

noasic

An open-source VHDL library for FPGA design.

✭ 27

VHDL Makefile fpga vhdl

formal hw verification

Trying to verify Verilog/VHDL designs with formal methods and tools

✭ 32

VHDL Makefile shell vhdl verilog ghdl formal-verification yosys psl symbiyosys

yavhdl

Yet Another VHDL tool

✭ 29

Yacc rust C++Lex VHDL python vhdl eda hdl

vim-hdl

Vim plugin to aid VHDL development (for LSP, see https://github.com/suoto/hdl_checker)

✭ 59

python Vim Script shell Dockerfile productivity vhdl vim-plugins verilog xilinx syntastic syntax-checker altera modelsim

OpenNAS

OpenN@S: Open-source software to NAS automatic VHDL code generation

✭ 15

C#VHDL Verilog python c vhdl spiking-neural-networks cochlea neuromorphic-hardware aedat neuromorphic-auditory-sensors neuromorphic-engineering opennas vhdl-generation

FPGA-I2C-Minion

A simple I2C minion in VHDL

✭ 50

VHDL Makefile i2c vhdl

vboard

Virtual development board for HDL design

✭ 32

VHDL python c Makefile shell vhdl verilog hdl ghdl cosim vpi verilator fli vhpidirect

Cache

Simple implementation of cache using VHDL

✭ 17

VHDL Makefile ram cache vhdl

SpinalCrypto

SpinalHDL - Cryptography libraries

✭ 36

scala java cryptography crypto fpga aes vhdl md5 sha rtl verilog crc hmac des spinalhdl

SiaFpgaMiner

VHDL FPGA design of an optimized Blake2b pipeline to mine Siacoin

✭ 58

VHDL python vhdl mining cryptocurrency blake2b siacoin

vhdl-hdmi-out

HDMI Out VHDL code for 7-series Xilinx FPGAs

✭ 36

VHDL Makefile fpga vhdl hdmi

BenEaterVHDL

VHDL project to run a simple 8-bit computer very similar to the one built by Ben Eater (see https://eater.net)

✭ 30

VHDL TeX Makefile cpu fpga vhdl uart sap-1 beneater

verilog-vcd-parser

A parser for Value Change Dump (VCD) files as specified in the IEEE System Verilog 1800-2012 standard.

✭ 46

C++Lex Makefile parser simulation vhdl trace verilog vcd

xeda

Cross EDA Abstraction and Automation

✭ 25

python tcl automation fpga hardware simulation vhdl eda verilog synthesis hdl

captouch

👇 Add capacitive touch buttons to any FPGA!

✭ 96

VHDL shell fpga vhdl button keypad capacitive-touch-sensor fomu

VHDLFormatter

VHDL formatter web online written in typescript

✭ 44

typescript HTML CSS VHDL javascript vhdl vhdl-formatter

Learning

@elahe-dastan / @1995parham training and testing repository 📚 🤓

✭ 53

vhdl sml

fpga torture

🔥 Technology-agnostic FPGA stress-test: maximum logic utilization and high dynamic power consumption.

✭ 23

VHDL shell fpga vhdl stress-testing power lfsr utilization

MSXPi

Interface for MSX to Connect and use Raspberry Pi resources

✭ 61

assembly c python shell VHDL basic raspberrypi vhdl z80 msx

vscode-terosHDL

VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!

✭ 325

javascript typescript HTML CSS python shell fpga vhdl verilog

SpinalDev

Docker Development Environment for SpinalHDL

✭ 17

Dockerfile shell dockerfile fpga vhdl rtl verilog spinalhdl

fpga-docker

Tools for running FPGA vendor toolchains with Docker

✭ 54

Makefile Dockerfile shell fpga vhdl verilog xilinx altera lattice quartus

121-144 of 144 vhdl projects

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