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Top 144 vhdl open source projects

Open Source Fpga Bitcoin Miner

A completely open source implementation of a Bitcoin Miner for Altera and Xilinx FPGAs. This project hopes to promote the free and open development of FPGA based mining solutions and secure the future of the Bitcoin project as a whole. A binary release is currently available for the Terasic DE2-115 Development Board, and there are compile-able projects for numerous boards.

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Digital FM Radio Receiver for FPGA

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Ophidian's Mirror Repository on github. https://gitlab.com/eclufsc/eda/ophidian

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cpp cpp11 cpp17 cpp14 open-source automation design embedded verilog research vhdl teaching eda

A package for Sublime Text that aids coding in the VHDL language.

✭ 31

python language emacs sublime-text vhdl

Image Processing

Image Processing Toolbox in Verilog using Basys3 FPGA

✭ 31

python python3 verilog fpga vhdl convolution pixel brightness

Haskell to VHDL/Verilog/SystemVerilog compiler

✭ 958

haskell verilog fpga vhdl asic

A lightweight, open source and FPGA-friendly 32-bit CPU core based on an original instruction set

✭ 27

assembly fpga cpu vhdl

Acorn BBC Micro on an Altera DE1 FPGA board

✭ 14

Vhdl Mips Pipeline Microprocessor

VHDL-Mips-Pipeline-Microprocessor

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Experimental compiler for a subset of Haskell to VHDL

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Simple custom computer on a FPGA

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AXI PSRAM Controller IP for use with Digilent Nexys 4

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AES-128 hardware implementation

✭ 25

cryptography fpga vhdl aes

Contains VHDL IP-blocks to create stand-alone RapidIO-endpoints, RapidIO-switches and RapidIO-switches with local endpoints.

✭ 23

Floating point library Jhu

VHDL for basic floating-point operations.

✭ 22

ASIO driver, Usb Driver, FX2LP Firmware, VHDL Fpga, Schematics & PCB Layout for the AudioXtreamer, a USB 2.0 32ch Audio/Midi interface for retrofitting into digital mixers/interfaces.

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c cpp fpga midi usb vhdl schematics asio

Hashvoodoo Fpga Bitcoin Miner

HashVoodoo FPGA Bitcoin Miner

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A Audio Interface for the Zedboard

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I2s Interface Vhdl

A simplified i2s interface taken from OpenCores' I2S Interface. Aimed for Altera Avalon Streaming interface.

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ECE368 | Lab

✭ 6

An implementation of original SHA-256 hash function in (RTL) VHDL

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operating-system cpu vhdl embedded-systems mips

A work-in-progress for what is to be a software-free web server for static content.

✭ 762

cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python

✭ 740

python verilog test vhdl verification

Scala based HDL

✭ 696

scala verilog fpga vhdl rtl

GPL v3 2D/3D graphics engine in verilog

✭ 515

VUnit is a unit testing framework for VHDL/SystemVerilog

✭ 438

unit-testing fpga vhdl verification asic

Parallella board design files

✭ 389

GameCube Digital AV converter

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Hardware Description Languages

✭ 385

hacktoberfest awesome awesome-list verilog vhdl

Parallella Examples

Community created parallella projects

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A tiny Open POWER ISA softcore written in VHDL 2008

✭ 383

verilog vhdl processor

Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators

✭ 356

qt debugger cpu simulator vhdl riscv

Core sources and tools for the MIST board

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VHDL compiler and simulator

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A 32-bit RISC-V / MIPS ISA retargetable CPU core & SoC, 1.63 DMIPS/MHz

✭ 338

arduino fpga vhdl riscv mips

Arduino MIPI DSI Shield

✭ 330

HAL – The Hardware Analyzer

✭ 298

security reverse-engineering hardware fpga vhdl

An abstraction library for interfacing EDA tools

✭ 270

python simulation verilog fpga vhdl eda synthesis

Open Source 4k CSI-2 Rx core for Xilinx FPGAs

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Reverse engineered SystemVerilog RTL version of the Yamaha OPL3 (YMF262) FM Synthesizer

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A simple three-stage RISC-V CPU

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VHDL tcl shell assembly c Makefile Batchfile fpga vhdl risc-v

SublimeText Plugin for VHDL (highlight, autocompletion, navigation, ...)

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python VHDL syntax-highlighting navigation vhdl tooltip hierarchy instantiation alignement

Fully pipelined Integer Scaled / Unscaled Radix-2 Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source language - VHDL / Verilog). GNU GPL 3.0.

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VHDL Verilog matlab fpga dsp vhdl verilog fast-fourier-transform xilinx fft vivado altera cooley-tukey-fft digital-signal-processing fast-convolutions radix-2 integer-arithmetic route-optimization

Scripts to build and use docker images including GHDL

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shell Dockerfile dockerfiles hardware ci simulation vhdl actions verilog synthesis icestorm gtkwave ghdl testbench vunit yosys openocd pnr nextpnr prjtrellis

🔑 Technology-agnostic Physical Unclonable Function (PUF) hardware module for any FPGA.

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VHDL c Makefile security fpga authentication vhdl fingerprint key-generation puf neorv32

VCD file (Value Change Dump) command line viewer

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c Makefile cli vhdl gtkwave vcd

VHDL/Verilog/SystemC code generator, simulator API written in python/c++

✭ 145

python simulator fpga compiler hls vhdl rtl verilog hcl codegenerator codegen systemc uvm

A list of VHDL codes implementing cryptographic algorithms

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VHDL Verilog cryptography aes vhdl ascon hardware-designs gimli cryptographic-primitive cryptographic-algorithms skinny block-ciphers

getting-started

List of ideas for getting started with TimVideos projects

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shell video university fpga usb electronics vhdl mjpeg projects verilog gsoc webcam hdmi usb-devices or1k gsoc-2016 risc-v gsoc-2017 hdmi2usb

Useful m-scripts for DSP (CIC, FIR, FFT, Fast convolution, Partial Filters etc.)

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matlab fpga math dsp vhdl octave verilog fast-fourier-transform fft digital-signal-processing fir fast-convolutions cic m-scripts

QNICE-FPGA is a 16-bit computer system for recreational programming built as a fully-fledged System-on-a-Chip in portable VHDL.

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assembly VHDL c shell HTML perl tutorial cpu fpga vhdl open-hardware fpga-game sd-card vga 16-bit soft-core system-on-chip vhdl-examples qnice learn-fpga fpga-tutorial vhdl-tutorial

This repository contains synthesizable examples which use the PoC-Library.

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VHDL fpga example vhdl synthesis poc-library

🔌 Hardware Abstraction Library in Python

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python hardware vhdl digital-modelling digital-systems

VHDL-2008 Support Library

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VHDL HTML hardware simulation vhdl verification synthesis fixed-point floating-point

Pre-packaged testbenching tools and reusable bus interfaces for cocotb

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python Verilog Makefile interface bus vhdl verilog hdl testbench cocotb

A JSON library implemented in VHDL.

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VHDL TeX powershell Batchfile parser json fpga simulation vhdl xilinx synthesis lattice fileformat modelsim questasim ghdl

Streaming based VHDL parser.

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python VHDL parser vhdl language-model

61-120 of 144 vhdl projects