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An Extended Version of the T0x multithreaded cores, with a custom general purpose parametrized SIMD/MIMD vector coprocessor and support for 3-5 way superscalar execution. The core is pin-to-pin compatible with the RISCY cores from PULP

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assembly c VHDL Verilog shell SystemVerilog accelerator simd riscv superscalar klessydra t02x t03x pulpino t13x vector-processor mimd

57. TinyFPGA-Bootloader

An open source USB bootloader for FPGAs

✭ 261

AGS Script HTML Verilog SystemVerilog python shell

58. uvm apb

uvm_apb is a uvm package for modeling and verifying APB (Advanced Periperal Bus) protocol

✭ 15

SystemVerilog

59. rare-disease-wf

(WIP) best-practices workflow for rare disease

✭ 47

Nextflow HTML SystemVerilog Dockerfile python genomics variants rare-disease

60. zerosoc

Demo SoC for SiliconCompiler.

✭ 37

Verilog python SystemVerilog

61. snitch

Lean but mean RISC-V system!

✭ 133

SystemVerilog c rust python Smarty tcl

62. RISCV CPU

A FPGA supported RISC-V CPU with 5-stage pipeline implemented in Verilog HDL

✭ 48

c Verilog C++assembly Coq SystemVerilog verilog-hdl risc-v

63. systemverilog-design-patterns

No description, website, or topics provided.

✭ 28

SystemVerilog shell

64. fpga-shells

No description, website, or topics provided.

✭ 115

scala Verilog SystemVerilog tcl Makefile

65. JSONinSV

JSON lib in Systemverilog

✭ 25

SystemVerilog json json-api json-parser

66. openc906

OpenXuantie - OpenC906 Core

✭ 161

Verilog assembly c SystemVerilog Makefile perl

67. openc910

OpenXuantie - OpenC910 Core

✭ 583

Verilog assembly c SystemVerilog Makefile V

68. pygears

HW Design: A Functional Approach

✭ 122

python Verilog Jinja SystemVerilog c shell design functional simulator asic fpga hardware hdl

69. RISCV Piccolo v1

Implementation of RISC-V RV32IM. Simple in-order 3-stage pipeline. Low resources (e.g., FPGA softcore).

✭ 29

Verilog c perl assembly Makefile C++SystemVerilog

70. thinpad top

Project template for Artix-7 based Thinpad board

✭ 39

Verilog c SystemVerilog python tcl

71. RFNoC-HLS-WINLAB

No description, website, or topics provided.

✭ 15

C++SystemVerilog Verilog c Makefile tcl

72. RiverRaidFPGA

River Raid game on FPGA

✭ 20

Verilog SystemVerilog Mathematica

73. parser

Derived from https://sourceforge.net/projects/v2kparse

✭ 44

java ANTLR ruby GAP SystemVerilog Verilog

74. sdram-controller

Generic FPGA SDRAM controller, originally made for AS4C4M16SA

✭ 45

Verilog SystemVerilog tcl python Stata fpga controller dram quartus sdram as4c4m16sa

75. Curso-Electronica-Digital-para-makers-con-FPGAs-Libres

Curso de 35h sobre el diseño de sistemas digitales usando FPGAs libres, orientado para makers

✭ 17

Verilog SystemVerilog course fpga fpgawars

76. stereo-vision-fpga

Real-time binocular stereo vision FPGA system with OV5640 cameras

✭ 20

tcl VHDL C++Verilog c objective c SystemVerilog fpga stereo-vision vivado-hls

77. FPGA NTP SERVER

A FPGA implementation of the NTP and NTS protocols

✭ 27

Verilog python c Makefile tcl shell SystemVerilog fpga verilog fpga-ntp-server

78. mksocfpga

Hostmot2 FPGA code for SoC/FPGA platforms from Altera and Xilinx

✭ 23

VHDL tcl SystemVerilog Makefile Verilog shell zynq fpga-platforms

79. pp-sp-reference-design

No description, website, or topics provided.

✭ 23

SystemVerilog c Makefile tcl

80. eddr3

mirror of https://git.elphel.com/Elphel/eddr3

✭ 33

Verilog SystemVerilog python HCL fpga zynq ddr verilog xilinx open-core ddr3 memory-controller

81. fpga fast serial sort

a parallel sorting algorithm implemented in hardware that sorts data in linear time as it arrives serially

✭ 32

SystemVerilog Makefile

82. amiq eth

Library defining all Ethernet packets in SystemVerilog and in SystemC

✭ 27

HTML C++SystemVerilog Makefile javascript CSS

83. tvip-axi

AMBA AXI VIP

✭ 129

SystemVerilog vip uvm axi amba axi4 amba-axi

84. Arcade-Galaga MiSTer

Arcade: Galaga for MiSTer

✭ 12

VHDL Verilog SystemVerilog tcl Batchfile

85. FpOC

FPGA-based Field Oriented Control (FOC) for driving BLDC/PMSM motor.

✭ 138

SystemVerilog Batchfile fpga motor verilog field-oriented-control bldc pmsm foc svpwm

86. PYNQ softmax

achieve softmax in PYNQ with heterogeneous computing.

✭ 38

VHDL Verilog SystemVerilog HTML c tcl

87. PYNQ Hackathon

Xilinx Hackathon 2017

✭ 16

Jupyter Notebook python Verilog HTML SystemVerilog CSS pynq

88. Superscalar-HIT-Core-NSCSCC2020

a Quad-issue, Out-of-order Superscalar MIPS Processor Implemented in SystemVerilog

✭ 32

SystemVerilog Verilog

89. sv-1800-2012

IEEE Std 1800™-2012: IEEE Standard for SystemVerilog -- Unified Hardware Design, Specification, and Verification Language syntax definition for VS Code

✭ 26

SystemVerilog

90. gateware

A collection of little open source FPGA hobby projects

✭ 38

SystemVerilog c C++Verilog Makefile Coq fpga ice40 ecp5 gateware

91. moxie-cores

Moxie-compatible core repository

✭ 43

Verilog VHDL c common lisp SystemVerilog tcl

92. iob-cache

Verilog configurable cache

✭ 76

Verilog Makefile TeX SystemVerilog tcl c

93. fpga design

这是我所开发的两个项目，包括ov5640-ddr3-usb2.0高速图像采集系统以及NOIP1SN1300A-ddr3-sdhc高速地表图像采集及存储系统

✭ 40

Verilog VHDL c HTML SystemVerilog tcl

94. Frix

IBM PC Compatible SoC for a commercially available FPGA board

✭ 48

Verilog VHDL SystemVerilog tcl shell Stata

95. mesm6

Implementation of BESM-6 clone in Verilog

✭ 37

pascal C++c SystemVerilog Verilog python

96. usb3 pipe

USB3 PIPE interface for Xilinx 7-Series

✭ 131

Verilog python c SystemVerilog

97. X68000 MiSTer

Sharp X68000 for MiSTer

✭ 51

VHDL Verilog SystemVerilog Roff

98. cluelib

A generic class library in SystemVerilog

✭ 59

HTML SystemVerilog javascript CSS Makefile TeX

99. blinky

Example LED blinking project for your FPGA dev board of choice

✭ 98

tcl Verilog VHDL SystemVerilog python Mathematica

100. UnarySim

This is a general-purpose simulator for unary computing based on PyTorch, with the paper accepted to ISCA 2020 and awarded IEEE Micro Top Pick for 2020.

✭ 20

SystemVerilog python simulation stochastic-computing temporal-computing rate-coding temporal-coding

51-100 of 227 SystemVerilog projects

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