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All Programming Languages → SystemVerilog

Top 227 SystemVerilog open source projects

101. INT FP MAC

INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.

✭ 31

Verilog SystemVerilog python tcl verilog uvm accumulator

102. risc-v-core

This project was done as a part of RISC-V based MYTH (Microprocessor for you in Thirty Hours) workshop organized by Kunal Ghosh and Steve Hoover

✭ 41

Verilog SystemVerilog tcl assembly

103. litesdcard

No description, website, or topics provided.

✭ 23

python Verilog c SystemVerilog Makefile

Hot & Spicy tool suite

✭ 21

python VHDL tcl Verilog SystemVerilog c

105. ZYNQ-NVDLA

NVDLA (An Opensource DL Accelerator Framework) implementation on FPGA.

✭ 144

Verilog c C++TeX Makefile SystemVerilog fpga zynq verilog nvdla yolox-nano

Network on Chip Implementation written in SytemVerilog

✭ 91

SystemVerilog Makefile fortran uvm noc axi amba network-on-chip axi4 amba-axi

FPGA Verilog implementation of 1949 EDSAC Computer with animated tape reader, panel, teleprinter and CRT scope

✭ 28

Verilog VHDL SystemVerilog Coq tcl shell fpga emulation verilog retrocomputing mister edsac vintage-computers papertape misterfpga

Reads a state transition system and performs property checking

✭ 41

C++Verilog SystemVerilog python shell Makefile verilog model-checking ic3 formal-verification pdr

pulp_soc is the core building component of PULP based SoCs

✭ 43

SystemVerilog riscv pulp

Cycle accurate MC6502 compatible processor in Verilog.

✭ 14

Verilog Limbo SystemVerilog Makefile ASL C++

111. bsg replicant

BSG Replicant: Cosimulation and Emulation Infrastructure for HammerBlade

✭ 22

C++Makefile SystemVerilog c Verilog tcl

112. SD-card-controller

WISHBONE SD Card Controller IP Core

✭ 77

Verilog SystemVerilog c Makefile

The Simple 5-staged pipeline RISC-V written in chisel3 for intel FPGA.

✭ 37

scala SystemVerilog tcl python assembly Makefile shell fpga intel chisel riscv chisel3 altera risc-v rv32i avalon-mm

Open source 10 Gigabit Ethernet MAC core compatible with Xilinx's non-free 10GMAC

✭ 42

Verilog SystemVerilog Makefile c tcl

115. mipsfpga-plus

MIPSfpga+ allows loading programs via UART and has a switchable clock

✭ 94

Verilog assembly Makefile tcl c SystemVerilog

repository for Vidor FPGA IP blocks and projects

✭ 74

Verilog tcl SystemVerilog Stata

An open-source GBA consolizer.

✭ 122

VHDL SystemVerilog C++python

A formally verified high-level synthesis tool based on CompCert and written in Coq.

✭ 63

Coq ocaml SystemVerilog scheme tcl shell semantics coq verification verilog compcert high-level-synthesis

119. MIPS54SP-Lifesaver

No description, website, or topics provided.

✭ 22

Verilog SystemVerilog assembly

120. soc-workshop

No description, website, or topics provided.

✭ 14

c tcl C++SystemVerilog shell Makefile

121. fpga-virtual-console

VT220-compatible console on Cyclone IV EP4CE55F23I7

✭ 33

SystemVerilog Verilog console keyboard terminal fpga vt100 terminal-emulator vt220 xterm-256color vt102 vt200

Website documenting a hardware project from the 1990s.

✭ 65

c HTML C++assembly Verilog SystemVerilog

123. BBCMicro MiSTer

BBC Micro B and Master 128K for MiSTer

✭ 18

VHDL Verilog SystemVerilog tcl Batchfile

124. Chisel-FFT-generator

FFT generator using Chisel

✭ 26

Verilog SystemVerilog scala tcl VHDL chisel fft rtl-generator

125. systemc-compiler

This tool translates synthesizable SystemC code to synthesizable SystemVerilog.

✭ 128

C++SystemVerilog Makefile shell CMake c hls llvm clang hardware-designs systemc

126. yosys2digitaljs

Export netlists from Yosys to DigitalJS

✭ 23

javascript SystemVerilog shell

Code to support porting MiST cores to other boards.

✭ 20

VHDL Verilog tcl c SystemVerilog Makefile shell

128. fpga-hash-table

Simple hash table on Verilog (SystemVerilog)

✭ 32

SystemVerilog Verilog

129. PSX MiSTer

PSX for MiSTer

✭ 122

VHDL Verilog SystemVerilog

This is the base repo for our graduation project in AlexU 21

✭ 29

SystemVerilog shell

131. Vivado-Design-Tutorials

No description, website, or topics provided.

✭ 59

tcl SystemVerilog Verilog c VHDL Jupyter Notebook

Limago: an FPGA-based Open-source 100 GbE TCP/IP Stack

✭ 95

tcl Verilog SystemVerilog c Makefile VHDL shell fpga tcp hls vivado network-stack vcu118 alveo-u200 100gbe alveo-u280

133. Hard-JPEG-LS

FPGA-based JPEG-LS image compressor.

✭ 52

SystemVerilog Batchfile fpga rtl verilog jpeg-ls jpegls jls

134. UltimateCart

SD-card multicart for Atari 8-bit computers

✭ 97

Eagle Verilog c SystemVerilog HTML VHDL

135. TangNano-9K-example

TangNano-9K-example project

✭ 73

GLSL Verilog HTML Coq SystemVerilog c

Generic Logic Interfacing Project

✭ 41

c Verilog tcl SystemVerilog C++M4

No description, website, or topics provided.

✭ 49

Verilog matlab C++SystemVerilog c

138. wav-lpddr-hw

Wavious DDR (WDDR) Physical interface (PHY) Hardware

✭ 65

SystemVerilog Verilog

139. BigComputeLabs

Big Compute Learning Labs

✭ 19

shell python SystemVerilog visualization genomics hpc azure gpu visualisation lab azure-batch labs rdma hpc-clusters big-compute azure-hpc

A realtime raytracing extension chip for the SNES

✭ 49

C#SystemVerilog Verilog assembly

Kronos is a 3-stage in-order RISC-V RV32I_Zicsr_Zifencei core geared towards FPGA implementations

✭ 38

SystemVerilog c CMake objective c perl C++

FPGA development platform for high-performance RF and digital design

✭ 27

VHDL KiCad Layout Verilog HTML tcl SystemVerilog

Shuhai is a benchmarking-memory tool that allows FPGA programmers to demystify all the underlying details of memories, e.g., HBM and DDR4, on a Xilinx FPGA

✭ 53

SystemVerilog c C++tcl Verilog Cuda benchmark fpga ddr hbm

144. Learn-FPGA-Programming

Learn FPGA Programming, published by Packt

✭ 81

VHDL Verilog V SystemVerilog tcl shell

This repo is for ECE44x (Fall2015-Spring2016)

✭ 17

SystemVerilog Verilog python shell PHP c fpga deep-learning cnn

146. Apple-II MiSTer

Apple II+ for MiSTer

✭ 33

VHDL Verilog SystemVerilog tcl Batchfile

147. vicii-kawari

Commodore 64 VIC-II 6567/6569 Replacement Project

✭ 43

Verilog c assembly C++Makefile SystemVerilog commodore commodore-64

148. ethernet 10ge mac SV tb

SystemVerilog testbench for an Ethernet 10GE MAC core

✭ 28

Verilog SystemVerilog Coq Makefile

149. Arcade-GnG MiSTer

Arcade Ghosts'n Goblins for MiSTer

✭ 15

Verilog VHDL SystemVerilog tcl Batchfile

150. XJTU-Tripler

XJTU-Tripler is based on HiPU100, an FPGA-friendly DNN accelerator, developed by CAG, Institute of AI & Robotics, XJTU.

✭ 159

VHDL c SystemVerilog Coq tcl Verilog

101-150 of 227 SystemVerilog projects