840 Open source projects that are alternatives of or similar to Axi

Various HDL (Verilog) IP Cores

A curated list of awesome open source hardware design tools

HW Design: A Functional Approach

Repository for basic (and not so basic) Verilog blocks with high re-use potential

Code generation tool for configuration and status registers

CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.

A low cost FPGA development board for absolute newbies

FPGA-based USB-device controller to implement USB-CDC, USB-HID, etc.

Open source ultrasound processing modules and building blocks

HAL – The Hardware Analyzer

SCR1 is a high-quality open-source RISC-V MCU core in Verilog

VUnit is a unit testing framework for VHDL/SystemVerilog

RISC-V Cores, SoC platforms and SoCs

32-bit Superscalar RISC-V CPU

Transient Array Radio Telescope

VHDL/Verilog/SystemC code generator, simulator API written in python/c++

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, Fault and custom methodology scripts for design exploration and optimization.

RISC-V CPU Core (RV32IM)

OpenLANE is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, Fault and custom methodology scripts for design exploration and optimization.

FireSim: Easy-to-use, Scalable, FPGA-accelerated Cycle-accurate Hardware Simulation in the Cloud

Video Game custom chips reverse-engineered from silicon

Simple, orthogonal 32-bit computer architecture and environment

Haskell to VHDL/Verilog/SystemVerilog compiler

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

Dynamically Allocated Neural Network Accelerator for the RISC-V Rocket Microprocessor in Chisel

Caffe to VHDL

SweRV EL2 Core

SystemRDL 2.0 language compiler front-end

Import and export IP-XACT XML register models

The Kria Robotics Stack (KRS) is a ROS 2 superset for industry, an integrated set of robot libraries and utilities to accelerate the development, maintenance and commercialization of industrial-grade robotic solutions while using adaptive computing.

WAL enables programmable waveform analysis.

FPGA CryptoNight V7 Minner

Generate UVM register model from compiled SystemRDL input

DFiant: A Dataflow Hardware Descripition Language

ROS 2 Hardware Acceleration Working Group community governance model & list of projects

Imitate SDcard using FPGAs.

Haskell library for hardware description

Connectal is a framework for software-driven hardware development.

A Just-In-Time Compiler for Verilog from VMware Research

SweRV EH1 core

Recipe for FPGA cooking

FPGA-based JPEG-LS image compressor.

An OpenCL-based FPGA Accelerator for Convolutional Neural Networks

Scala based HDL

PlatformIO IDE for VSCode: The next generation integrated development environment for IoT

Tool to generate register RTL, models, and docs using SystemRDL or JSpec input

All open source file and project for OpenFPGAduino project

FPGA-based RISC-V CPU+SoC.

The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

Kactus2 is a graphical EDA tool based on the IP-XACT standard.

collection of works aiming at reducing model sizes or the ASIC/FPGA accelerator for machine learning

Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation

A small and customizable full-scale 32-bit RISC-V soft-core CPU and SoC written in platform-independent VHDL.

Verilog implementation of the symmetric block cipher AES (Advanced Encryption Standard) as specified in NIST FIPS 197. This implementation supports 128 and 256 bit keys.

Scots Army Knife for electronics

SpinalHDL - Cryptography libraries

Intel 8080-based Space Invaders arcade machine implemented on an FPGA, written in CLaSH

PlatformIO IDE for Atom: The next generation integrated development environment for IoT

GPGPU microprocessor architecture

Space Invaders game implemented with VHDL