1090 Open source projects that are alternatives of or similar to Darkriscv

FPGA-based RISC-V CPU+SoC.

SweRV EH1 core

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SweRV EL2 Core

SCR1 is a high-quality open-source RISC-V MCU core in Verilog

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KianRISC-V! No RISC-V, no fun! RISC-V CPU with strong design rules and unittested! CPU you can trust! kianv rv32im risc-v a hdmi soc with harris computer architecture in verilog: multicycle, singlecycle and 5-stage pipelining Processor. Multicycle Soc with firmware that runs raytracer, mandelbrot, 3d hdmi gfx, dma controller, etc.....

This repository hosts the project for open-source hummingbird E203 RISC processor Core.

RISC-V processor emulator written in Rust+WASM

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A FPGA friendly 32 bit RISC-V CPU implementation

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A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain( chisel, mill, verilator, NEMU, AM and difftest framework, etc) to design and verify.

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CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.

Repository for basic (and not so basic) Verilog blocks with high re-use potential

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FPGA 101 - Workshop materials

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The next generation integrated development environment for processor design and verification. It has multi-hardware language support, open source IP management and easy-to-use rtl simulation toolset.

Show the time on a VGA monitor. Submitted for the Google MPW1 ASIC shuttle.

F# RISC-V Instruction Set formal specification

Imitate SDcard using FPGAs.

List of ideas for getting started with TimVideos projects

Portable games console, designed from scratch: CPU, graphics, PCB, and the kitchen sink

Small Processing Unit 32: A compact RV32I CPU written in Verilog

Sphinx Extension which generates various types of diagrams from Verilog code.

SpinalHDL - Cryptography libraries

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A reimplementation of a tiny stack CPU

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

FPGA-based JPEG-LS image compressor.

The Simple 5-staged pipeline RISC-V written in chisel3 for intel FPGA.

ARV: Asynchronous RISC-V Go High-level Functional Model

PlatformIO is a professional collaborative platform for embedded development 👽 A place where Developers and Teams have true Freedom! No more vendor lock-in!

Virtio implementation in SystemVerilog

A hardware implementation of CNN, written by Verilog and synthesized on FPGA

Materials for "Introduction to FPGA and Verilog" at MIPT DREC

A MIPS CPU implemented in Verilog

VHDL/Verilog/SystemC code generator, simulator API written in python/c++

FPGA-based USB-device controller to implement USB-CDC, USB-HID, etc.

Yet another toy CPU.

Quasar 2.0: Chisel equivalent of SweRV-EL2

A small, light weight, RISC CPU soft core

A re-creation of a Cosmac ELF computer, Coded in SpinalHDL

Fuxi (伏羲) is a 32-bit pipelined RISC-V processor written in Chisel3.

Homebrew game for homebrew FPGA game console

Haskell library for hardware description

An abstraction library for interfacing EDA tools

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OpenROAD's unified application implementing an RTL-to-GDS Flow

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A self-hosting and educational C compiler