901 Open source projects that are alternatives of or similar to E200_opensource

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

32-bit Superscalar RISC-V CPU

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SCR1 is a high-quality open-source RISC-V MCU core in Verilog

FPGA-based RISC-V CPU+SoC.

LicheeTang 蜂鸟E203 Core

A small, light weight, RISC CPU soft core

This ARMv4-compatible CPU core is written in synthesiable verilog.It could launch uCLinux and Linux in MODELSIM. It has high Dhrystone benchmark value: 1.2 DMIPS/MHz. It could be utilized in your FPGA design as one submodule, if you master the interface of this .v file. This IP core is very compact. It is one .v file and has only less 1800 lines.

Cycle-accurate pre-silicon simulator of RISC-V and MIPS CPUs

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Simple 3-stage pipeline RISC-V processor

Human Resource Machine - CPU Design #HRM

A crazy small 8-bit CPU built with only seventeen 7400-series chips.

Yet another toy CPU.

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RISC-V CPU Core

F# RISC-V Instruction Set formal specification

KianRISC-V! No RISC-V, no fun! RISC-V CPU with strong design rules and unittested! CPU you can trust! kianv rv32im risc-v a hdmi soc with harris computer architecture in verilog: multicycle, singlecycle and 5-stage pipelining Processor. Multicycle Soc with firmware that runs raytracer, mandelbrot, 3d hdmi gfx, dma controller, etc.....

Riscv32 CPU Project

8051 soft CPU core. 700-lines statements for 111 instructions . Fully synthesizable Verilog-2001 core.

Homebrew game for homebrew FPGA game console

RISC-V processor emulator written in Rust+WASM

Nuclei Microcontroller Software Interface Standard Development Repo

PlatformIO is a professional collaborative platform for embedded development 👽 A place where Developers and Teams have true Freedom! No more vendor lock-in!

RT-Thread is an open source IoT operating system.

Small Processing Unit 32: A compact RV32I CPU written in Verilog

支持 45 条 MIPS 指令的单周期处理器 -- 计算机组成原理实验 NUAA Spring 2017

Yet Another RISC-V Implementation

A picorv32-riscv Soc with DMAC and Ethernet controller & lwip & Kirtex7@333MHz

A FPGA friendly 32 bit RISC-V CPU implementation

Riscy-SoC is SoC based on RISC-V CPU core, designed in Verilog

A reimplementation of a tiny stack CPU

All CPU and MCU documentation in one place

Portable games console, designed from scratch: CPU, graphics, PCB, and the kitchen sink

Featherweight RISC-V implementation

Nuclei RISC-V Software Development Kit

A MIPS CPU implemented in Verilog

Compact FPGA game console

A small and customizable full-scale 32-bit RISC-V soft-core CPU and SoC written in platform-independent VHDL.

oneAPI Math Kernel Library (oneMKL) Interfaces

🌱 ❄️ Collection of open-source peripherals in Verilog

Assesses CPU security of embedded devices. #nsacyber

NES in Verilog

FPGA based acceleration of Convolutional Neural Networks. The project is developed by Verilog for Altera DE5 Net platform.

Verilog HDL/SystemVerilog/Bluespec SystemVerilog support for VS Code

SystemVerilog language server

Open source, headless, multi-tenant eCommerce platform built with .NET Core, MongoDB, AWS DocumentDB, Azure CosmosDB, Vue.js.

An imperative and functional programming language

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Acceleration package for neural networks on multi-core CPUs

SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST API.

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Connectal is a framework for software-driven hardware development.

The Higher-Order Intermediate Representation

A simple, basic, formally verified UART controller

SoC design for Milkymist One - LM32, DDR SDRAM, 2D TMU, PFPU

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