1339 Open source projects that are alternatives of or similar to getting-started

720p FPGA Media Player (RISC-V + Motion JPEG + SD + HDMI on an Artix 7)

Compact FPGA game console

Useful m-scripts for DSP (CIC, FIR, FFT, Fast convolution, Partial Filters etc.)

FPGA-based USB-device controller to implement USB-CDC, USB-HID, etc.

Materials for "Introduction to FPGA and Verilog" at MIPT DREC

Cross EDA Abstraction and Automation

Fully pipelined Integer Scaled / Unscaled Radix-2 Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source language - VHDL / Verilog). GNU GPL 3.0.

LicheeTang 蜂鸟E203 Core

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

Scala based HDL

A reimplementation of a tiny stack CPU

A simple three-stage RISC-V CPU

SpinalHDL - Cryptography libraries

An abstraction library for interfacing EDA tools

Small Processing Unit 32: A compact RV32I CPU written in Verilog

Haskell to VHDL/Verilog/SystemVerilog compiler

High throughput JPEG decoder in Verilog for FPGA

Tools for running FPGA vendor toolchains with Docker

VHDL/Verilog/SystemC code generator, simulator API written in python/c++

Yet Another RISC-V Implementation

RISC-V CPU Core (RV32IM)

A FPGA friendly 32 bit RISC-V CPU implementation

ASIO driver, Usb Driver, FX2LP Firmware, VHDL Fpga, Schematics & PCB Layout for the AudioXtreamer, a USB 2.0 32ch Audio/Midi interface for retrofitting into digital mixers/interfaces.

32-bit Superscalar RISC-V CPU

Implementation of a Tensor Processing Unit for embedded systems and the IoT.

Docker Development Environment for SpinalHDL

bl_mcu_sdk is MCU software development kit provided by Bouffalo Lab Team for BL602/BL604, BL702/BL704/BL706, BL616/BL618, BL808 and other series of RISC-V based chips in the future.

Image Processing Toolbox in Verilog using Basys3 FPGA

A small and customizable full-scale 32-bit RISC-V soft-core CPU and SoC written in platform-independent VHDL.

HDMI Out VHDL code for 7-series Xilinx FPGAs

Various HDL (Verilog) IP Cores

PlatformIO is a professional collaborative platform for embedded development 👽 A place where Developers and Teams have true Freedom! No more vendor lock-in!

Homebrew game for homebrew FPGA game console

FPGA-based RISC-V CPU+SoC.

VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!

A full-speed device-side USB peripheral core written in Verilog.

A parser for Value Change Dump (VCD) files as specified in the IEEE System Verilog 1800-2012 standard.

Programmable multichannel ADPCM decoder for FPGA

🔮 Word by word audio subtitle synchronisation tool and API. Developed under GSoC 2017 with CCExtractor.

A programming language for FPGAs.

Lattice iCE40: development platform for PlatformIO

PhyWhisperer-USB: Hardware USB Trigger

No-MMU Linux capable RISC-V SoC designed to be useful.

Hardware definition library and environment for designing and building digital hardware for FPGAs, using only open source tools

RISC-V Cores, SoC platforms and SoCs

A hardware implementation of CNN, written by Verilog and synthesized on FPGA

Virtio implementation in SystemVerilog

This repository contains iCEBreaker examples for Amaranth HDL.

MOS6581 SID chip emulator in SystemVerilog

Sphinx Extension which generates various types of diagrams from Verilog code.

Simple 3-stage pipeline RISC-V processor

An Verilog implementation of 7-to-1 LVDS Serializer. Which can be used for comunicating FPGAs with LVDS TFT Screens.

Generator of verilog description for FPGA MobileNet implementation

Drop In USB CDC ACM core for iCE40 FPGA

Fake News Detection Final Year College Project with Project Report, PPT, Code, Research Paper and Documents.

👇 Add capacitive touch buttons to any FPGA!

VHDL project to run a simple 8-bit computer very similar to the one built by Ben Eater (see https://eater.net)

A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog

Virtual development board for HDL design

FPGA-based JPEG-LS image compressor.