1673 Open source projects that are alternatives of or similar to hwt

Docker Development Environment for SpinalHDL

Virtio implementation in SystemVerilog

SpinalHDL - Cryptography libraries

Recipe for FPGA cooking

Scala based HDL

FPGA-based RISC-V CPU+SoC.

Imitate SDcard using FPGAs.

An abstraction library for interfacing EDA tools

Fully pipelined Integer Scaled / Unscaled Radix-2 Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source language - VHDL / Verilog). GNU GPL 3.0.

FPGA/hardware design of openwifi

Implementation of a Tensor Processing Unit for embedded systems and the IoT.

Sphinx Extension which generates various types of diagrams from Verilog code.

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

Haskell library for hardware description

Haskell to VHDL/Verilog/SystemVerilog compiler

Useful m-scripts for DSP (CIC, FIR, FFT, Fast convolution, Partial Filters etc.)

A FPGA friendly 32 bit RISC-V CPU implementation

FPGA-based JPEG-LS image compressor.

A reimplementation of a tiny stack CPU

open-source IEEE 802.11 WiFi baseband FPGA (chip) design

Various HDL (Verilog) IP Cores

Repository for basic (and not so basic) Verilog blocks with high re-use potential

Code generation tool for configuration and status registers

Image Processing Toolbox in Verilog using Basys3 FPGA

A Forth CPU and System on a Chip, based on the J1, written in VHDL

Tools for running FPGA vendor toolchains with Docker

Show the time on a VGA monitor. Submitted for the Google MPW1 ASIC shuttle.

Cross EDA Abstraction and Automation

A hardware implementation of CNN, written by Verilog and synthesized on FPGA

FPGA-based USB-device controller to implement USB-CDC, USB-HID, etc.

CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.

VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!

List of ideas for getting started with TimVideos projects

Lattice iCE40: development platform for PlatformIO

Materials for "Introduction to FPGA and Verilog" at MIPT DREC

A translator Django into SQLAlchemy.

A parser for Value Change Dump (VCD) files as specified in the IEEE System Verilog 1800-2012 standard.

A template for simple C++ reflection done with CMake and Python (no other external tools)

Hardware definition library and environment for designing and building digital hardware for FPGAs, using only open source tools

A Hardware Construct Language

Facilitates building open source tools for working with hardware description languages (HDLs)

VHDL project to run a simple 8-bit computer very similar to the one built by Ben Eater (see https://eater.net)

Programmable multichannel ADPCM decoder for FPGA

OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/

Small Processing Unit 32: A compact RV32I CPU written in Verilog

FPGA core for SHA256d mining targeting Lattice iCE40 devices.

MOS6581 SID chip emulator in SystemVerilog

Typescript DSL for GraphQL.

A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog

HDMI Out VHDL code for 7-series Xilinx FPGAs

An Verilog implementation of 7-to-1 LVDS Serializer. Which can be used for comunicating FPGAs with LVDS TFT Screens.

Generator of verilog description for FPGA MobileNet implementation

Virtual development board for HDL design

Wishbone controlled I2C controllers

A programming language for FPGAs.

PDP-6 Emulator

Limago: an FPGA-based Open-source 100 GbE TCP/IP Stack

This tool translates synthesizable SystemC code to synthesizable SystemVerilog.

Pipelined implementation of Sobel Edge Detection on OV7670 camera and on still images

Vim plugin to aid VHDL development (for LSP, see https://github.com/suoto/hdl_checker)