1170 Open source projects that are alternatives of or similar to Logic

RISC-V CPU Core (RV32IM)

Code generation tool for configuration and status registers

Various HDL (Verilog) IP Cores

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VUnit is a unit testing framework for VHDL/SystemVerilog

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

Sphinx Extension which generates various types of diagrams from Verilog code.

Haskell to VHDL/Verilog/SystemVerilog compiler

Video Game custom chips reverse-engineered from silicon

Verilog implementation of the symmetric block cipher AES (Advanced Encryption Standard) as specified in NIST FIPS 197. This implementation supports 128 and 256 bit keys.

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

Scala based HDL

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FPGA-based JPEG-LS image compressor.

FPGA-based RISC-V CPU+SoC.

A hardware implementation of CNN, written by Verilog and synthesized on FPGA

Recipe for FPGA cooking

Haskell library for hardware description

Docker Development Environment for SpinalHDL

Show the time on a VGA monitor. Submitted for the Google MPW1 ASIC shuttle.

SpinalHDL - Cryptography libraries

Virtio implementation in SystemVerilog

FPGA-based USB-device controller to implement USB-CDC, USB-HID, etc.

Imitate SDcard using FPGAs.

Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation

Repository for basic (and not so basic) Verilog blocks with high re-use potential

VHDL/Verilog/SystemC code generator, simulator API written in python/c++

OpenLANE is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, Fault and custom methodology scripts for design exploration and optimization.

Tool to generate register RTL, models, and docs using SystemRDL or JSpec input

All open source file and project for OpenFPGAduino project

Learn how to design digital systems and synthesize them into an FPGA using only opensource tools

Verilog to Routing -- Open Source CAD Flow for FPGA Research

FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.

RISC-V Cores, SoC platforms and SoCs

PlatformIO IDE for Atom: The next generation integrated development environment for IoT

PlatformIO is a professional collaborative platform for embedded development 👽 A place where Developers and Teams have true Freedom! No more vendor lock-in!

The USRP™ Hardware Driver Repository

A small, light weight, RISC CPU soft core

A Just-In-Time Compiler for Verilog from VMware Research

collection of works aiming at reducing model sizes or the ASIC/FPGA accelerator for machine learning

PlatformIO IDE for VSCode: The next generation integrated development environment for IoT

HDL libraries and projects

❄️ Visual editor for open FPGA boards

Intermediate Representation Of Hardware Abstraction (LLVM-ish for HLS)

LicheeTang 蜂鸟E203 Core

A bare bones, basic, ZipCPU system designed for both testing and quick integration into new systems

Image Processing Toolbox in Verilog using Basys3 FPGA

A simple, basic, formally verified UART controller

Scalable systolic array-based matrix-matrix multiplication implemented in Vivado HLS for Xilinx FPGAs.

A MIPS CPU implemented in Verilog

🤖 SoCFPGA: Open Source embedded Linux developed for Intel (ALTERA) SoC-FPGAs (Cyclone V & Arria 10)

SweRV EH1 core

cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python

This is a higan/Verilator co-simulation example/framework

Human Resource Machine - CPU Design #HRM

A collection of extensions for Vivado HLS and Intel FPGA OpenCL to improve developer quality of life.

A mixed signal netlist language (pre-alpha)

FPGA 101 - Workshop materials

A reimplementation of a tiny stack CPU