585 Open source projects that are alternatives of or similar to Openpiton

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

SystemOT, yet another home brew cpu.

FPGA-based USB-device controller to implement USB-CDC, USB-HID, etc.

🌟 IceZUM Alhambra: an Arduino-like Open FPGA electronic board

Cross EDA Abstraction and Automation

Verilog FPGA Parts Library. Old Octavo soft-CPU project.

Sphinx Extension which generates various types of diagrams from Verilog code.

MOS6581 SID chip emulator in SystemVerilog

A FPGA implementation of the NTP and NTS protocols

Imitate SDcard using FPGAs.

Various HDL (Verilog) IP Cores

Video Game custom chips reverse-engineered from silicon

Yet Another Tetris on FPGA Implementation

Materials for "Introduction to FPGA and Verilog" at MIPT DREC

A programming language for FPGAs.

Minimal SDR with Lattice MachXO2 FPGA. And a port to Cyclone3 by Steven Groom

Small Processing Unit 32: A compact RV32I CPU written in Verilog

Generator of verilog description for FPGA MobileNet implementation

A hardware implementation of CNN, written by Verilog and synthesized on FPGA

Pipelined implementation of Sobel Edge Detection on OV7670 camera and on still images

FPGA Verilog implementation of 1949 EDSAC Computer with animated tape reader, panel, teleprinter and CRT scope

mirror of https://git.elphel.com/Elphel/eddr3

NVDLA (An Opensource DL Accelerator Framework) implementation on FPGA.

An FPGA implementation of a classic 80ies speech synthesizer. Done for the Retro Challenge 2017/10.

Fully pipelined Integer Scaled / Unscaled Radix-2 Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source language - VHDL / Verilog). GNU GPL 3.0.

Wishbone controlled I2C controllers

【原创，已被编入官方教材】Three-level storage subsystem(SD+DDR2 SDRAM+Cache), based on Nexys4 FPGA board. 同济大学计算机系统结构课程设计，FPGA三级存储子系统。

VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!

A collection of phase locked loop (PLL) related projects

A re-creation of a Cosmac ELF computer, Coded in SpinalHDL

Robotic Application Processor

Programmable multichannel ADPCM decoder for FPGA

Lattice iCE40: development platform for PlatformIO

Show the time on a VGA monitor. Submitted for the Google MPW1 ASIC shuttle.

Global Dark Mode for ALL apps on ANY platforms.

Virtio implementation in SystemVerilog

VHDL/Verilog/SystemC code generator, simulator API written in python/c++

Hardware definition library and environment for designing and building digital hardware for FPGAs, using only open source tools

A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog

An Verilog implementation of 7-to-1 LVDS Serializer. Which can be used for comunicating FPGAs with LVDS TFT Screens.

SpinalHDL - Cryptography libraries

The next generation integrated development environment for processor design and verification. It has multi-hardware language support, open source IP management and easy-to-use rtl simulation toolset.

Yet Another RISC-V Implementation

Fork of OpenVeriFla - FPGA debugging logic analyzer to use with your designs - examples (so far) for ice40/IceStorm

List of ideas for getting started with TimVideos projects

NN on FPGA

FPGA-based Field Oriented Control (FOC) for driving BLDC/PMSM motor.

Karuta HLS Compiler: High level synthesis from prototype based object oriented script language to RTL (Verilog) aiming to be useful for FPGA development.

EVEREST: e-Versatile Research Stick for peoples

PDP-6 Emulator

FPGA core for SHA256d mining targeting Lattice iCE40 devices.

An abstraction library for interfacing EDA tools

Useful m-scripts for DSP (CIC, FIR, FFT, Fast convolution, Partial Filters etc.)

A configurable C++ generator of pipelined Verilog FFT cores

Homebrew game for homebrew FPGA game console

Docker Development Environment for SpinalHDL

KianRISC-V! No RISC-V, no fun! RISC-V CPU with strong design rules and unittested! CPU you can trust! kianv rv32im risc-v a hdmi soc with harris computer architecture in verilog: multicycle, singlecycle and 5-stage pipelining Processor. Multicycle Soc with firmware that runs raytracer, mandelbrot, 3d hdmi gfx, dma controller, etc.....

FPGA-based JPEG-LS image compressor.

A full-speed device-side USB peripheral core written in Verilog.

RISC-V CPU Core (RV32IM)