650 Open source projects that are alternatives of or similar to Spi Fpga

Scala based HDL

A FPGA friendly 32 bit RISC-V CPU implementation

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List of ideas for getting started with TimVideos projects

A simple three-stage RISC-V CPU

Space Invaders game implemented with VHDL

Fletcher: A framework to integrate FPGA accelerators with Apache Arrow

Haskell to VHDL/Verilog/SystemVerilog compiler

QNICE-FPGA is a 16-bit computer system for recreational programming built as a fully-fledged System-on-a-Chip in portable VHDL.

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SpinalHDL - Cryptography libraries

🔥 Technology-agnostic FPGA stress-test: maximum logic utilization and high dynamic power consumption.

A JSON library implemented in VHDL.

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A small and customizable full-scale 32-bit RISC-V soft-core CPU and SoC written in platform-independent VHDL.

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Image Processing Toolbox in Verilog using Basys3 FPGA

HDMI Out VHDL code for 7-series Xilinx FPGAs

This repository contains synthesizable examples which use the PoC-Library.

An open-source VHDL library for FPGA design.

An abstraction library for interfacing EDA tools

Various HDL (Verilog) IP Cores

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🔑 Technology-agnostic Physical Unclonable Function (PUF) hardware module for any FPGA.

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ASIO driver, Usb Driver, FX2LP Firmware, VHDL Fpga, Schematics & PCB Layout for the AudioXtreamer, a USB 2.0 32ch Audio/Midi interface for retrofitting into digital mixers/interfaces.

Useful m-scripts for DSP (CIC, FIR, FFT, Fast convolution, Partial Filters etc.)

Generic FPGA SDRAM controller, originally made for AS4C4M16SA

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Implementation of a Tensor Processing Unit for embedded systems and the IoT.

AES-128 hardware implementation

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A very small msp430-compatible customizable soft-core microcontroller-like processor system written in platform-independent VHDL.

Caffe to VHDL

VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!

VHDL/Verilog/SystemC code generator, simulator API written in python/c++

A 32-bit RISC-V / MIPS ISA retargetable CPU core & SoC, 1.63 DMIPS/MHz

A lightweight, open source and FPGA-friendly 32-bit CPU core based on an original instruction set

Automatic GPU, TPU, FPGA, Xeon Phi, Multithreaded, Distributed, etc. offloading for scientific machine learning (SciML) and differential equations

Example code for the Numato Opsis board, the first HDMI2USB production board.

Acorn BBC Micro on an Altera DE1 FPGA board

VHDL-Mips-Pipeline-Microprocessor

A MIPS CPU implemented in Verilog

Experimental compiler for a subset of Haskell to VHDL

A completely open source implementation of a Bitcoin Miner for Altera and Xilinx FPGAs. This project hopes to promote the free and open development of FPGA based mining solutions and secure the future of the Bitcoin project as a whole. A binary release is currently available for the Terasic DE2-115 Development Board, and there are compile-able projects for numerous boards.

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Mirror of https://codeberg.org/ECP5-PCIe/ECP5-PCIe

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Simple, orthogonal 32-bit computer architecture and environment

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Donjon hardware tool for circuits security evaluation