785 Open source projects that are alternatives of or similar to Zipcpu

A reimplementation of a tiny stack CPU

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

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A MIPS CPU implemented in Verilog

RISC-V CPU Core (RV32IM)

32-bit Superscalar RISC-V CPU

A FPGA friendly 32 bit RISC-V CPU implementation

FPGA-based RISC-V CPU+SoC.

KianRISC-V! No RISC-V, no fun! RISC-V CPU with strong design rules and unittested! CPU you can trust! kianv rv32im risc-v a hdmi soc with harris computer architecture in verilog: multicycle, singlecycle and 5-stage pipelining Processor. Multicycle Soc with firmware that runs raytracer, mandelbrot, 3d hdmi gfx, dma controller, etc.....

This ARMv4-compatible CPU core is written in synthesiable verilog.It could launch uCLinux and Linux in MODELSIM. It has high Dhrystone benchmark value: 1.2 DMIPS/MHz. It could be utilized in your FPGA design as one submodule, if you master the interface of this .v file. This IP core is very compact. It is one .v file and has only less 1800 lines.

Pipelined implementation of Sobel Edge Detection on OV7670 camera and on still images

PlatformIO is a professional collaborative platform for embedded development 👽 A place where Developers and Teams have true Freedom! No more vendor lock-in!

The Project TinyMIPS is dedicated to enabling undergraduates to build a complete computer system from scratch.

PDP-6 Emulator

NonTrivial-MIPS is a synthesizable superscalar MIPS processor with branch prediction and FPU support, and it is capable of booting linux.

NN on FPGA

A Just-In-Time Compiler for Verilog from VMware Research

8051 soft CPU core. 700-lines statements for 111 instructions . Fully synthesizable Verilog-2001 core.

The USRP™ Hardware Driver Repository

A configurable C++ generator of pipelined Verilog FFT cores

NVDLA (An Opensource DL Accelerator Framework) implementation on FPGA.

A FPGA implementation of the NTP and NTS protocols

QNICE-FPGA is a 16-bit computer system for recreational programming built as a fully-fledged System-on-a-Chip in portable VHDL.

Useful m-scripts for DSP (CIC, FIR, FFT, Fast convolution, Partial Filters etc.)

FPGA-based USB-device controller to implement USB-CDC, USB-HID, etc.

Robotic Application Processor

PlatformIO IDE for Atom: The next generation integrated development environment for IoT

FPGA-based JPEG-LS image compressor.

SpinalHDL - Cryptography libraries

ROS 2 Hardware Acceleration Working Group community governance model & list of projects

Generator of verilog description for FPGA MobileNet implementation

Yet Another RISC-V Implementation

Fork of OpenVeriFla - FPGA debugging logic analyzer to use with your designs - examples (so far) for ice40/IceStorm

FPGA Verilog implementation of 1949 EDSAC Computer with animated tape reader, panel, teleprinter and CRT scope

A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog

FPGA-based Field Oriented Control (FOC) for driving BLDC/PMSM motor.

Karuta HLS Compiler: High level synthesis from prototype based object oriented script language to RTL (Verilog) aiming to be useful for FPGA development.

mirror of https://git.elphel.com/Elphel/eddr3

A crazy small 8-bit CPU built with only seventeen 7400-series chips.

Fuxi (伏羲) is a 32-bit pipelined RISC-V processor written in Chisel3.

A full-speed device-side USB peripheral core written in Verilog.

Wishbone controlled I2C controllers

An Verilog implementation of 7-to-1 LVDS Serializer. Which can be used for comunicating FPGAs with LVDS TFT Screens.

Global Dark Mode for ALL apps on ANY platforms.

Minimal SDR with Lattice MachXO2 FPGA. And a port to Cyclone3 by Steven Groom

A collection of phase locked loop (PLL) related projects

VHDL/Verilog/SystemC code generator, simulator API written in python/c++

An FPGA implementation of a classic 80ies speech synthesizer. Done for the Retro Challenge 2017/10.

Homebrew game for homebrew FPGA game console

Fully pipelined Integer Scaled / Unscaled Radix-2 Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source language - VHDL / Verilog). GNU GPL 3.0.

🌱 Open source ecosystem for open FPGA boards

List of ideas for getting started with TimVideos projects

Video Game custom chips reverse-engineered from silicon

Haskell library for hardware description

Verilog to Routing -- Open Source CAD Flow for FPGA Research

Various HDL (Verilog) IP Cores

🌟 IceZUM Alhambra: an Arduino-like Open FPGA electronic board

Repository for basic (and not so basic) Verilog blocks with high re-use potential

An abstraction library for interfacing EDA tools

The OpenPiton Platform