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Implementing 32 Verilog Mini Projects. 32 bit adder, Array Multiplier, Barrel Shifter, Binary Divider 16 by 8, Booth Multiplication, CRC Coding, Carry Select and Carry Look Ahead Adder, Carry Skip and Carry Save Adder, Complex Multiplier, Dice Game, FIFO, Fixed Point Adder and Subtractor, Fixed Point Multiplier and Divider, Floating Point IEEE 7…

✭ 66

Verilog python verilog verilog-hdl miniproject verilog-project

59. SSBCC

Small Stack-Based Computer Compiler -- Verilog micro controller for FPGA housekeeping with peripherals

✭ 15

python Verilog assembly shell HTML Roff

60. ofdm

Chisel Things for OFDM

✭ 23

scala python C++shell Makefile assembly Verilog chip-generator chisel rtl chisel3 firrtl verilog

61. UART2NAND

Interface for exposing raw NAND i/o over UART to enable pc-side modification.

✭ 20

Verilog python

62. SOFA

SOFA (Skywater Opensource FPGAs) based on Skywater 130nm PDK and OpenFPGA

✭ 55

Verilog tcl python shell Makefile c

63. Cello-v2

Cello v2 is the continuation of the Cello genetic circuit design software.

✭ 31

java Verilog python synthetic-biology cello genetic-circuit-design-automation bio-design-automation

64. wasca

Sega Saturn multipurporse cartridge

✭ 40

c Verilog SystemVerilog VHDL assembly Makefile

65. intfftk

Fully pipelined Integer Scaled / Unscaled Radix-2 Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source language - VHDL / Verilog). GNU GPL 3.0.

✭ 43

VHDL Verilog matlab fpga dsp vhdl verilog fast-fourier-transform xilinx fft vivado altera cooley-tukey-fft digital-signal-processing fast-convolutions radix-2 integer-arithmetic route-optimization

66. Speech256

An FPGA implementation of a classic 80ies speech synthesizer. Done for the Retro Challenge 2017/10.

✭ 51

Verilog python fpga speech synthesizer verilog hdl retrochallenge

67. TMR

Triple Modular Redundancy

✭ 16

Verilog tcl VHDL c shell assembly

68. MiSTery

Atari ST/STe core for MiST

✭ 27

Verilog SystemVerilog VHDL Makefile atari-st

69. i3c-slave-design

MIPI I3C Basic v1.0 communication Slave source code in Verilog with BSD license to support use in sensors and other devices.

✭ 50

Verilog

70. vdatp

Volumetric Display using an Acoustically Trapped Particle

✭ 86

Verilog HTML C++SystemVerilog c python

71. VGChips

Video Game custom chips reverse-engineered from silicon

✭ 86

Verilog asic fpga reverse-engineering arcade verilog chip hdl silicon cpld repro taito decap

72. SBusFPGA

Stuff to put a FPGA in a SBus system (SPARCstation)

✭ 26

python c Verilog VHDL forth rust

73. Hardware Design

No description, website, or topics provided.

✭ 25

Verilog

74. clockwork

A polyhedral compiler for hardware accelerators

✭ 39

C++c Verilog SystemVerilog Makefile python

75. OpenGL-Programming-Guide-8th-Edition-Code

No description, website, or topics provided.

✭ 33

c C++GLSL GAP V Verilog

76. iceglitch

cheap and terrible voltage glitcher hardware/software

✭ 28

python Verilog Jupyter Notebook c Makefile shell

77. vp awsfpga

Virtual Platform for AWS FPGA support

✭ 14

Verilog SystemVerilog c C++tcl Makefile

78. PlayStation MiSTer

PlayStation for MiSTer FPGA

✭ 180

VHDL Verilog SystemVerilog tcl

79. dpll

A collection of phase locked loop (PLL) related projects

✭ 55

Verilog C++matlab Makefile shell fpga gplv3 verilog verilator pll

80. bitcoin mining

Simple test fpga bitcoin miner

✭ 20

Verilog shell python Batchfile tcl Stata

81. usb2 dev

USB 2.0 Device IP Core

✭ 28

Verilog

82. ce2020labs

ChipEXPO 2020 Digital Design School Labs

✭ 22

javascript Verilog SystemVerilog CSS HTML shell

83. rygar-fpga

A FPGA core for the arcade game, Rygar (1986).

✭ 17

VHDL Verilog SystemVerilog c Coq tcl game fpga arcade mister rygar

84. rapcores

Robotic Application Processor

✭ 14

Verilog c Makefile Nix C++shell fpga robotics verilog cnc motors 3d-printing

85. router

清华大学2019计网联合实验第一组

✭ 27

VHDL Coq V Verilog assembly SystemVerilog

86. Atari800 MiSTer

Atari 800XL/65XE/130XE for MiSTer

✭ 23

VHDL Verilog SystemVerilog c assembly tcl

87. sdaccel chisel integration

Chisel Project for Integrating RTL code into SDAccel

✭ 18

Verilog scala C++Makefile python

88. DIPSY

No description, website, or topics provided.

✭ 22

C++pascal VHDL Verilog python

89. hardenedlinux profiles

It contains hardenedlinux community documentation.

✭ 57

Verilog

90. vdf-fpga

Implementation of an RSA VDF evaluator targeting FPGAs.

✭ 41

SystemVerilog tcl python C++Makefile Verilog

91. icestick

Simple demo for Lattice iCEstick board as seen on Hackaday

✭ 16

Verilog shell

92. UMDCTF-2017-Challenges

A selection of challenges created for UMDCTF 2017

✭ 23

ruby Verilog

93. verilog-wishbone

Verilog wishbone components

✭ 67

python Verilog

94. lambdasoc

No description, website, or topics provided.

✭ 32

python C++Verilog

95. FreePDK45-RRAM-Addon

A RRAM addon for the NCSU FreePDK 45nm

✭ 12

HTML VHDL python perl HCL Verilog

96. Deep-DarkFantasy

Global Dark Mode for ALL apps on ANY platforms.

✭ 16

Verilog tcl SystemVerilog Makefile shell javascript fpga zynq dark-theme verilog xilinx vivado verilog-hdl dark-mode zynq-7000 dark-mode-toggle

97. TPU-Tensor-Processing-Unit

IC implementation of TPU

✭ 32

Verilog rust tcl Batchfile typescript shell

98. Clarinet

A RISC-V processor written in BSV, based on the Flute core. Has support for integrating tightly-coupled accelerators, and for integrating custom functional units like posit arithmetic units.

✭ 14

Bluespec c python Verilog Makefile C++

99. VossII

The source code to the Voss II Hardware Verification Suite

✭ 19

Verilog c tcl Yacc haskell Makefile

100. 1bitSDR

Minimal SDR with Lattice MachXO2 FPGA. And a port to Cyclone3 by Steven Groom

✭ 53

VHDL Verilog HTML c SystemVerilog V fpga ham-radio amateur-radio verilog sdr lattice lattice-machxo2

51-100 of 626 Verilog projects

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