348 Open source projects that are alternatives of or similar to ProjectOberon2013

Oberon-07 translator

Oberon-07 compiler for x64 (Windows, Linux), x86 (Windows, Linux, KolibriOS), MSP430x{1,2}xx, STM32 Cortex-M3

SpinalHDL - Cryptography libraries

A pipelined implementation of the MIPS processor featuring hazard detection as well as forwarding

Here are my solutions to HDLbits Verilog problem sets (HDLbits: https://hdlbits.01xz.net/wiki/Main_Page).

PDP-6 Emulator

HDLBits website practices & solutions

Simple 3-stage pipeline RISC-V processor

Sphinx Extension which generates various types of diagrams from Verilog code.

A Hardware Construct Language

Vim plugin to aid VHDL development (for LSP, see https://github.com/suoto/hdl_checker)

Lattice iCE40: development platform for PlatformIO

🔧 Verilog plugin for Sublime Text 2/3. It helps to generate a simple testbench, instantiate a module, insert a user-header, repeat codes with formatted incremental/decremental numbers, etc.

A crazy small 8-bit CPU built with only seventeen 7400-series chips.

Virtual development board for HDL design

8051 soft CPU core. 700-lines statements for 111 instructions . Fully synthesizable Verilog-2001 core.

A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog

FPGA Verilog implementation of 1949 EDSAC Computer with animated tape reader, panel, teleprinter and CRT scope

FAST-9 Accelerator for Corner Detection

PCIe (1.0a to 2.0) Virtual host model for verilog

Virtio implementation in SystemVerilog

Trying to verify Verilog/VHDL designs with formal methods and tools

Hardware definition library and environment for designing and building digital hardware for FPGAs, using only open source tools

Karuta HLS Compiler: High level synthesis from prototype based object oriented script language to RTL (Verilog) aiming to be useful for FPGA development.

A parser for Value Change Dump (VCD) files as specified in the IEEE System Verilog 1800-2012 standard.

Python Verilog value change dump (VCD) parser library + the nifty vcdcat VCD command line pretty printer.

A programming language for FPGAs.

A formally verified high-level synthesis tool based on CompCert and written in Coq.

Revengineered ancient PDP-11 CPUs, originals and clones

This ARMv4-compatible CPU core is written in synthesiable verilog.It could launch uCLinux and Linux in MODELSIM. It has high Dhrystone benchmark value: 1.2 DMIPS/MHz. It could be utilized in your FPGA design as one submodule, if you master the interface of this .v file. This IP core is very compact. It is one .v file and has only less 1800 lines.

HDL symbol generator

FPGA-based JPEG-LS image compressor.

INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.

Oberon Microsystems BlackBox Component Builder port for OpenBSD, GNU/Linux and FreeBSD

A full-speed device-side USB peripheral core written in Verilog.

Generator of verilog description for FPGA MobileNet implementation

NVDLA (An Opensource DL Accelerator Framework) implementation on FPGA.

An Verilog implementation of 7-to-1 LVDS Serializer. Which can be used for comunicating FPGAs with LVDS TFT Screens.

Verilog (SystemVerilog) coding style

MOS6581 SID chip emulator in SystemVerilog

Reads a state transition system and performs property checking

Pre-packaged testbenching tools and reusable bus interfaces for cocotb

Small Processing Unit 32: A compact RV32I CPU written in Verilog

Standard Cell Library based Memory Compiler using FF/Latch cells

Facilitates building open source tools for working with hardware description languages (HDLs)

FPGA-based Field Oriented Control (FOC) for driving BLDC/PMSM motor.

OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/

Pipelined implementation of Sobel Edge Detection on OV7670 camera and on still images

A hardware implementation of CNN, written by Verilog and synthesized on FPGA

A FPGA implementation of the NTP and NTS protocols

Materials for "Introduction to FPGA and Verilog" at MIPT DREC

Yet Another RISC-V Implementation

Programmable multichannel ADPCM decoder for FPGA

Bazel build rules for Verilator

Cross EDA Abstraction and Automation

Fork of OpenVeriFla - FPGA debugging logic analyzer to use with your designs - examples (so far) for ice40/IceStorm

Verilog grammar for tree-sitter

BlackBox Cross-Platform (Windows, GNU/Linux, OpenBSD, FreeBSD)

mirror of https://git.elphel.com/Elphel/eddr3

Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.