811 Open source projects that are alternatives of or similar to Scr1

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

FPGA-based RISC-V CPU+SoC.

SweRV EH1 core

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

Yet Another RISC-V Implementation

SweRV EL2 Core

This repository hosts the project for open-source hummingbird E203 RISC processor Core.

The next generation integrated development environment for processor design and verification. It has multi-hardware language support, open source IP management and easy-to-use rtl simulation toolset.

A hardware implementation of CNN, written by Verilog and synthesized on FPGA

A Hardware Construct Language

Sphinx Extension which generates various types of diagrams from Verilog code.

RISC-V Assembler and Runtime Simulator

KianRISC-V! No RISC-V, no fun! RISC-V CPU with strong design rules and unittested! CPU you can trust! kianv rv32im risc-v a hdmi soc with harris computer architecture in verilog: multicycle, singlecycle and 5-stage pipelining Processor. Multicycle Soc with firmware that runs raytracer, mandelbrot, 3d hdmi gfx, dma controller, etc.....

Materials for "Introduction to FPGA and Verilog" at MIPT DREC

Show the time on a VGA monitor. Submitted for the Google MPW1 ASIC shuttle.

OpenROAD's unified application implementing an RTL-to-GDS Flow

SoC based on VexRiscv and ICE40 UP5K

Facilitates building open source tools for working with hardware description languages (HDLs)

FPGA-based JPEG-LS image compressor.

Simple 3-stage pipeline RISC-V processor

Nuclei RISC-V Software Development Kit

Yet another toy CPU.

Simple risc-v emulator, able to run linux, written in C.

RISC-V RV32I[MAC] emulator with ELF support

MDEPX — A BSD-style RTOS

Imitate SDcard using FPGAs.

A picorv32-riscv Soc with DMAC and Ethernet controller & lwip & Kirtex7@333MHz

Shakti: development platform for PlatformIO

A self-hosting and educational C compiler

Docker Development Environment for SpinalHDL

A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain( chisel, mill, verilator, NEMU, AM and difftest framework, etc) to design and verify.

RISC-V Instruction Set Metadata

OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/

32-bit Superscalar RISC-V CPU

RISC-V CPU Core (RV32IM)

Small Processing Unit 32: A compact RV32I CPU written in Verilog

Maxine VM: A meta-circular research VM

Virtio implementation in SystemVerilog

Various HDL (Verilog) IP Cores

SpinalHDL - Cryptography libraries

A System Level RISCV32 Emulator Over x86_64: capable of booting RISCV Linux

Recipe for FPGA cooking

The Simple 5-staged pipeline RISC-V written in chisel3 for intel FPGA.

Sedna - a pure Java RISC-V emulator.

RISC-V processor emulator written in Rust+WASM

A RISC-V simulator

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, Fault and custom methodology scripts for design exploration and optimization.

Add right-to-left support to the NativeScript framework

Repository for basic (and not so basic) Verilog blocks with high re-use potential

ARV: Asynchronous RISC-V Go High-level Functional Model

List of ideas for getting started with TimVideos projects

Test suite designed to check compliance with the SystemVerilog standard.

OpenLANE is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, Fault and custom methodology scripts for design exploration and optimization.

FPGA-based USB-device controller to implement USB-CDC, USB-HID, etc.

Nuclei Microcontroller Software Interface Standard Development Repo

Chisel Things for OFDM

VHDL/Verilog/SystemC code generator, simulator API written in python/c++

Homebrew game for homebrew FPGA game console

Haskell library for hardware description

Quasar 2.0: Chisel equivalent of SweRV-EL2