850 Open source projects that are alternatives of or similar to Speech256

Hardware definition library and environment for designing and building digital hardware for FPGAs, using only open source tools

Video Game custom chips reverse-engineered from silicon

Cross EDA Abstraction and Automation

Virtio implementation in SystemVerilog

Sphinx Extension which generates various types of diagrams from Verilog code.

A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog

Yet Another Tetris on FPGA Implementation

shdl6800: A 6800 processor written in SpinalHDL

Lattice iCE40: development platform for PlatformIO

Robotic Application Processor

MOS6581 SID chip emulator in SystemVerilog

This repository contains iCEBreaker examples for Amaranth HDL.

An Verilog implementation of 7-to-1 LVDS Serializer. Which can be used for comunicating FPGAs with LVDS TFT Screens.

FPGA-based USB-device controller to implement USB-CDC, USB-HID, etc.

【原创，已被编入官方教材】Three-level storage subsystem(SD+DDR2 SDRAM+Cache), based on Nexys4 FPGA board. 同济大学计算机系统结构课程设计，FPGA三级存储子系统。

Global Dark Mode for ALL apps on ANY platforms.

Materials for "Introduction to FPGA and Verilog" at MIPT DREC

FPGA core for SHA256d mining targeting Lattice iCE40 devices.

Small Processing Unit 32: A compact RV32I CPU written in Verilog

Wishbone controlled I2C controllers

A hardware implementation of CNN, written by Verilog and synthesized on FPGA

PDP-6 Emulator

NN on FPGA

Yet Another RISC-V Implementation

NVDLA (An Opensource DL Accelerator Framework) implementation on FPGA.

Pipelined implementation of Sobel Edge Detection on OV7670 camera and on still images

Revengineered ancient PDP-11 CPUs, originals and clones

Karuta HLS Compiler: High level synthesis from prototype based object oriented script language to RTL (Verilog) aiming to be useful for FPGA development.

VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!

Show the time on a VGA monitor. Submitted for the Google MPW1 ASIC shuttle.

List of ideas for getting started with TimVideos projects

KianRISC-V! No RISC-V, no fun! RISC-V CPU with strong design rules and unittested! CPU you can trust! kianv rv32im risc-v a hdmi soc with harris computer architecture in verilog: multicycle, singlecycle and 5-stage pipelining Processor. Multicycle Soc with firmware that runs raytracer, mandelbrot, 3d hdmi gfx, dma controller, etc.....

Programmable multichannel ADPCM decoder for FPGA

A programming language for FPGAs.

Docker Development Environment for SpinalHDL

Minimal SDR with Lattice MachXO2 FPGA. And a port to Cyclone3 by Steven Groom

Facilitates building open source tools for working with hardware description languages (HDLs)

A FPGA implementation of the NTP and NTS protocols

Useful m-scripts for DSP (CIC, FIR, FFT, Fast convolution, Partial Filters etc.)

VHDL/Verilog/SystemC code generator, simulator API written in python/c++

Tools for running FPGA vendor toolchains with Docker

A full-speed device-side USB peripheral core written in Verilog.

HW Design: A Functional Approach

FPGA-based JPEG-LS image compressor.

Virtual development board for HDL design

Fork of OpenVeriFla - FPGA debugging logic analyzer to use with your designs - examples (so far) for ice40/IceStorm

SpinalHDL - Cryptography libraries

A configurable C++ generator of pipelined Verilog FFT cores

FPGA Verilog implementation of 1949 EDSAC Computer with animated tape reader, panel, teleprinter and CRT scope

Generator of verilog description for FPGA MobileNet implementation

mirror of https://git.elphel.com/Elphel/eddr3

Web-based HDL diagramming tool

Pre-packaged testbenching tools and reusable bus interfaces for cocotb

HDL symbol generator

CNN acceleration on virtex-7 FPGA with verilog HDL

Must-have verilog systemverilog modules

A collection of phase locked loop (PLL) related projects

FPGA-based Field Oriented Control (FOC) for driving BLDC/PMSM motor.

Homebrew game for homebrew FPGA game console

DFiant: A Dataflow Hardware Descripition Language