922 Open source projects that are alternatives of or similar to sphinxcontrib-hdl-diagrams

Test suite designed to check compliance with the SystemVerilog standard.

Virtio implementation in SystemVerilog

Hardware definition library and environment for designing and building digital hardware for FPGAs, using only open source tools

FPGA-based JPEG-LS image compressor.

Imitate SDcard using FPGAs.

FPGA-based RISC-V CPU+SoC.

Show the time on a VGA monitor. Submitted for the Google MPW1 ASIC shuttle.

Haskell library for hardware description

Web-based HDL diagramming tool

A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog

FPGA-based USB-device controller to implement USB-CDC, USB-HID, etc.

CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.

Facilitates building open source tools for working with hardware description languages (HDLs)

Video Game custom chips reverse-engineered from silicon

Various HDL (Verilog) IP Cores

A hardware implementation of CNN, written by Verilog and synthesized on FPGA

Cross EDA Abstraction and Automation

FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.

Code generation tool for configuration and status registers

Recipe for FPGA cooking

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, Fault and custom methodology scripts for design exploration and optimization.

VHDL/Verilog/SystemC code generator, simulator API written in python/c++

SpinalHDL - Cryptography libraries

Repository for basic (and not so basic) Verilog blocks with high re-use potential

Scala based HDL

An FPGA implementation of a classic 80ies speech synthesizer. Done for the Retro Challenge 2017/10.

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

Docker Development Environment for SpinalHDL

SweRV EL2 Core

A Hardware Construct Language

Small Processing Unit 32: A compact RV32I CPU written in Verilog

The Antikernel operating system project

Compact FPGA game console

FPGA Assembly (FASM) Parser and Generator

A utility for Composing FPGA designs from Peripherals

GPGPU microprocessor architecture

OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/

Example designs showing different ways to use SymbiFlow toolchains.

A Video display simulator

Box of handy tools for Sphinx 🧰 📔

shdl6800: A 6800 processor written in SpinalHDL

Connectal is a framework for software-driven hardware development.

Tool to generate register RTL, models, and docs using SystemRDL or JSpec input

i8080 precise replica in Verilog, based on reverse engineering of real die

Verilog implementation of the symmetric block cipher AES (Advanced Encryption Standard) as specified in NIST FIPS 197. This implementation supports 128 and 256 bit keys.

A simple, basic, formally verified UART controller

Programmable multichannel ADPCM decoder for FPGA

Lattice iCE40: development platform for PlatformIO

A programming language for FPGAs.

CAPCOM arcade hardware accurately replicated on MiST and MiSTer FPGA platforms. It covers Ghosts'n Goblins, 1942, 1943, Commando, F1-Dream, GunSmoke, Tiger Road, Black Tiger, Bionic Commando, Higemaru, Street Fighter and Vulgus.

Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation

LicheeTang 蜂鸟E203 Core

All open source file and project for OpenFPGAduino project

Sphinx extension to show tooltips with content embedded when hover a reference.

CHIP-8 console on FPGA

FPGA/hardware design of openwifi

Implementation of a Tensor Processing Unit for embedded systems and the IoT.

Bus bridges and other odds and ends

Verilog Generator of Neural Net Digit Detector for FPGA

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication