fpga torture🔥 Technology-agnostic FPGA stress-test: maximum logic utilization and high dynamic power consumption.
polyphonyPolyphony is Python based High-Level Synthesis compiler.
tiny-tpuSmall-scale Tensor Processing Unit built on an FPGA
vscode-terosHDLVHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!
soap🎯 soap - Structural Optimisation of Arithmetic Programs
FPGAmp720p FPGA Media Player (RISC-V + Motion JPEG + SD + HDMI on an Artix 7)
FPGACosmacELFA re-creation of a Cosmac ELF computer, Coded in SpinalHDL
vga-clockShow the time on a VGA monitor. Submitted for the Google MPW1 ASIC shuttle.
kianRiscVKianRISC-V! No RISC-V, no fun! RISC-V CPU with strong design rules and unittested! CPU you can trust! kianv rv32im risc-v a hdmi soc with harris computer architecture in verilog: multicycle, singlecycle and 5-stage pipelining Processor. Multicycle Soc with firmware that runs raytracer, mandelbrot, 3d hdmi gfx, dma controller, etc.....
Awesome-Retro-DocsA curated collection of technical documentation for Arcades, Handhelds, Consoles, Computers and MCU’s.
basic-ecp5-pcbReference design for Lattice ECP5 FPGA. Featuring Raspberry Pi interface and 6 PMODs
SpinalDevDocker Development Environment for SpinalHDL
fpga-dockerTools for running FPGA vendor toolchains with Docker