Cheap and reliable Node.js hosting starts at $3/month, and $1/month static HTML hosting

iBioSim is a computer-aided design (CAD) tool aimed for the modeling, analysis, and design of genetic circuits. It is capable of importing and exporting models specified using the Systems Biology Markup Language (SBML). iBioSim also supports the Synthetic Biology Open Language (SBOL), an emerging standard for information exchange in synthetic bi…

✭ 46

java GAP perl ANTLR Verilog shell

131. HPS2FPGAmapping

SoCFPGA: Mapping HPS Peripherals, like I²C or CAN, over the FPGA fabric to FPGA I/O and using embedded Linux to control them (Intel Cyclone V)

✭ 27

Verilog linux fpga python-script intel bootloader altera can-bus fpga-soc embedded-linux quartus-prime intel-fpga altera-fpga hps fpga-configuration soc-fpga fpga-fabric mapping-hps-peripherals rsyocto

132. riscv-invicta

A simple RISC-V core, described with Verilog

✭ 22

Verilog assembly

133. dsi controller

MIPI DSI controller

✭ 37

HTML Verilog SystemVerilog tcl shell Makefile

134. Clio

Clio, ASPLOS'22.

✭ 37

c tcl Verilog scala C++HTML fpga disaggregation spinalhdl libibverbs

135. daisho

SuperSpeed USB 3.0 FPGA platform

✭ 238

Eagle Verilog python c C++Makefile

136. sincos

Efficient implementations of the transcendental functions

✭ 22

forth python Verilog c verilog

137. CompilerDesignInC

Allen Holub's Book 'Compiler Design In C' source code

✭ 18

c Yacc Makefile Lex Verilog C++shell

138. UA3REO-DDC-Transceiver

DDC/DUC SDR Tranceiver project

✭ 93

c HTML VHDL Verilog tcl assembly fpga dsp stm32 sdr trx ddc rf notch duc

139. antikernel-ipcores

FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations

✭ 41

SystemVerilog Verilog

140. shapool-core

FPGA core for SHA256d mining targeting Lattice iCE40 devices.

✭ 19

Verilog c python Makefile shell SystemVerilog fpga bitcoin verilog sha256 icestorm ice40 lattice-fpga

141. phywhispererusb

PhyWhisperer-USB: Hardware USB Trigger

✭ 56

VHDL Verilog V c SystemVerilog python fpga usb glitch oshw hardware-triggering

142. chipfail-glitcher

No description, website, or topics provided.

✭ 55

SystemVerilog Verilog Coq Jupyter Notebook VHDL assembly shell

143. idea

iDEA FPGA Soft Processor

✭ 14

Verilog assembly python c shell Stata

144. wbi2c

Wishbone controlled I2C controllers

✭ 25

Verilog C++Lex Makefile c shell assembly fpga i2c gplv3 verilog verilator i2c-slave wishbone-bus i2c-master

145. Digital-IDE

在vscode上的fpga开发插件

✭ 78

VHDL Verilog V javascript tcl Makefile

146. beagle

BeagleBone HW, SW, & FPGA Development

✭ 46

Verilog C++c shell

147. VerilogLanguageExtension

Verilog Language Extension for Visual Studio

✭ 16

C#Verilog Coq Makefile vsix verilog visual-studio-extension

148. T13x

An Extended Version of the T0x multithreaded cores, with a custom general purpose parametrized SIMD/MIMD vector coprocessor and support for 3-5 way superscalar execution. The core is pin-to-pin compatible with the RISCY cores from PULP

✭ 28

assembly c VHDL Verilog shell SystemVerilog accelerator simd riscv superscalar klessydra t02x t03x pulpino t13x vector-processor mimd

149. rosetta

Rapidly deploy Chisel and Vivado HLS accelerators on Xilinx PYNQ

✭ 28

tcl scala C++Verilog Makefile c

150. bedrock

Coq library for verified low-level programming

✭ 37

Coq Makefile c assembly Verilog ocaml

101-150 of 626 Verilog projects