607 Open source projects that are alternatives of or similar to blarney

Virtio implementation in SystemVerilog

A hardware implementation of CNN, written by Verilog and synthesized on FPGA

Docker Development Environment for SpinalHDL

SpinalHDL - Cryptography libraries

Code generation tool for configuration and status registers

FPGA-based JPEG-LS image compressor.

Sphinx Extension which generates various types of diagrams from Verilog code.

Recipe for FPGA cooking

FPGA-based USB-device controller to implement USB-CDC, USB-HID, etc.

Various HDL (Verilog) IP Cores

Scala based HDL

FPGA-based RISC-V CPU+SoC.

Show the time on a VGA monitor. Submitted for the Google MPW1 ASIC shuttle.

Repository for basic (and not so basic) Verilog blocks with high re-use potential

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

Imitate SDcard using FPGAs.

CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.

VHDL/Verilog/SystemC code generator, simulator API written in python/c++

Homebrew game for homebrew FPGA game console

KianRISC-V! No RISC-V, no fun! RISC-V CPU with strong design rules and unittested! CPU you can trust! kianv rv32im risc-v a hdmi soc with harris computer architecture in verilog: multicycle, singlecycle and 5-stage pipelining Processor. Multicycle Soc with firmware that runs raytracer, mandelbrot, 3d hdmi gfx, dma controller, etc.....

VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!

A programming language for FPGAs.

【原创，已被编入官方教材】Three-level storage subsystem(SD+DDR2 SDRAM+Cache), based on Nexys4 FPGA board. 同济大学计算机系统结构课程设计，FPGA三级存储子系统。

Programmable multichannel ADPCM decoder for FPGA

Video Game custom chips reverse-engineered from silicon

OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/

A Hardware Construct Language

A collection of phase locked loop (PLL) related projects

Tools for running FPGA vendor toolchains with Docker

Must-have verilog systemverilog modules

Cross EDA Abstraction and Automation

Yet Another Tetris on FPGA Implementation

Materials for "Introduction to FPGA and Verilog" at MIPT DREC

CNN acceleration on virtex-7 FPGA with verilog HDL

List of ideas for getting started with TimVideos projects

Hardware definition library and environment for designing and building digital hardware for FPGAs, using only open source tools

Facilitates building open source tools for working with hardware description languages (HDLs)

MOS6581 SID chip emulator in SystemVerilog

Lattice iCE40: development platform for PlatformIO

FPGA core for SHA256d mining targeting Lattice iCE40 devices.

An Verilog implementation of 7-to-1 LVDS Serializer. Which can be used for comunicating FPGAs with LVDS TFT Screens.

Robotic Application Processor

Small Processing Unit 32: A compact RV32I CPU written in Verilog

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

Useful m-scripts for DSP (CIC, FIR, FFT, Fast convolution, Partial Filters etc.)

Wishbone controlled I2C controllers

NN on FPGA

PDP-6 Emulator

Fork of OpenVeriFla - FPGA debugging logic analyzer to use with your designs - examples (so far) for ice40/IceStorm

Pipelined implementation of Sobel Edge Detection on OV7670 camera and on still images

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, Fault and custom methodology scripts for design exploration and optimization.

Chisel Things for OFDM

Generator of verilog description for FPGA MobileNet implementation

Yet Another RISC-V Implementation

FPGA Verilog implementation of 1949 EDSAC Computer with animated tape reader, panel, teleprinter and CRT scope

Global Dark Mode for ALL apps on ANY platforms.

Minimal SDR with Lattice MachXO2 FPGA. And a port to Cyclone3 by Steven Groom

FPGA-based Field Oriented Control (FOC) for driving BLDC/PMSM motor.

A configurable C++ generator of pipelined Verilog FFT cores

A FPGA implementation of the NTP and NTS protocols