614 Open source projects that are alternatives of or similar to Fake-SDcard

A hardware implementation of CNN, written by Verilog and synthesized on FPGA

Show the time on a VGA monitor. Submitted for the Google MPW1 ASIC shuttle.

FPGA-based USB-device controller to implement USB-CDC, USB-HID, etc.

Sphinx Extension which generates various types of diagrams from Verilog code.

Repository for basic (and not so basic) Verilog blocks with high re-use potential

Virtio implementation in SystemVerilog

VHDL/Verilog/SystemC code generator, simulator API written in python/c++

Recipe for FPGA cooking

SpinalHDL - Cryptography libraries

FPGA-based JPEG-LS image compressor.

Scala based HDL

FPGA-based RISC-V CPU+SoC.

Docker Development Environment for SpinalHDL

Various HDL (Verilog) IP Cores

Code generation tool for configuration and status registers

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.

Haskell library for hardware description

Global Dark Mode for ALL apps on ANY platforms.

Minimal SDR with Lattice MachXO2 FPGA. And a port to Cyclone3 by Steven Groom

VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!

Cross EDA Abstraction and Automation

【原创，已被编入官方教材】Three-level storage subsystem(SD+DDR2 SDRAM+Cache), based on Nexys4 FPGA board. 同济大学计算机系统结构课程设计，FPGA三级存储子系统。

A programming language for FPGAs.

Chisel Things for OFDM

Fully pipelined Integer Scaled / Unscaled Radix-2 Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source language - VHDL / Verilog). GNU GPL 3.0.

OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/

An FPGA implementation of a classic 80ies speech synthesizer. Done for the Retro Challenge 2017/10.

KianRISC-V! No RISC-V, no fun! RISC-V CPU with strong design rules and unittested! CPU you can trust! kianv rv32im risc-v a hdmi soc with harris computer architecture in verilog: multicycle, singlecycle and 5-stage pipelining Processor. Multicycle Soc with firmware that runs raytracer, mandelbrot, 3d hdmi gfx, dma controller, etc.....

Homebrew game for homebrew FPGA game console

Materials for "Introduction to FPGA and Verilog" at MIPT DREC

Facilitates building open source tools for working with hardware description languages (HDLs)

List of ideas for getting started with TimVideos projects

Test suite designed to check compliance with the SystemVerilog standard.

Yet Another Tetris on FPGA Implementation

Programmable multichannel ADPCM decoder for FPGA

Tools for running FPGA vendor toolchains with Docker

Hardware definition library and environment for designing and building digital hardware for FPGAs, using only open source tools

A Hardware Construct Language

Lattice iCE40: development platform for PlatformIO

Small Processing Unit 32: A compact RV32I CPU written in Verilog

Must-have verilog systemverilog modules

Generator of verilog description for FPGA MobileNet implementation

PDP-6 Emulator

Video Game custom chips reverse-engineered from silicon

NN on FPGA

A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog

FPGA core for SHA256d mining targeting Lattice iCE40 devices.

Yet Another RISC-V Implementation

Pipelined implementation of Sobel Edge Detection on OV7670 camera and on still images

Useful m-scripts for DSP (CIC, FIR, FFT, Fast convolution, Partial Filters etc.)

An Verilog implementation of 7-to-1 LVDS Serializer. Which can be used for comunicating FPGAs with LVDS TFT Screens.

Fork of OpenVeriFla - FPGA debugging logic analyzer to use with your designs - examples (so far) for ice40/IceStorm

A collection of phase locked loop (PLL) related projects

Wishbone controlled I2C controllers

FPGA-based Field Oriented Control (FOC) for driving BLDC/PMSM motor.

Karuta HLS Compiler: High level synthesis from prototype based object oriented script language to RTL (Verilog) aiming to be useful for FPGA development.

mirror of https://git.elphel.com/Elphel/eddr3

Robotic Application Processor

NVDLA (An Opensource DL Accelerator Framework) implementation on FPGA.