426 Open source projects that are alternatives of or similar to sv-tests

Verilog grammar for tree-sitter

Fork of OpenVeriFla - FPGA debugging logic analyzer to use with your designs - examples (so far) for ice40/IceStorm

A crazy small 8-bit CPU built with only seventeen 7400-series chips.

HDLBits website practices & solutions

Homebrew game for homebrew FPGA game console

FPGA Verilog implementation of 1949 EDSAC Computer with animated tape reader, panel, teleprinter and CRT scope

A configurable C++ generator of pipelined Verilog FFT cores

Reads a state transition system and performs property checking

Minimal SDR with Lattice MachXO2 FPGA. And a port to Cyclone3 by Steven Groom

Standard Cell Library based Memory Compiler using FF/Latch cells

Ruby interface to IEEE 1364-2005 Verilog VPI

sb-admin2-rtl is a RTL version of the Bootstrap based admin theme SB Admin 2.

Implementing 32 Verilog Mini Projects. 32 bit adder, Array Multiplier, Barrel Shifter, Binary Divider 16 by 8, Booth Multiplication, CRC Coding, Carry Select and Carry Look Ahead Adder, Carry Skip and Carry Save Adder, Complex Multiplier, Dice Game, FIFO, Fixed Point Adder and Subtractor, Fixed Point Multiplier and Divider, Floating Point IEEE 7…

Pipelined implementation of Sobel Edge Detection on OV7670 camera and on still images

A right-to-left theme for Jekyll with Jalali support and some other goodies.

Vim plugin to aid VHDL development (for LSP, see https://github.com/suoto/hdl_checker)

A formally verified high-level synthesis tool based on CompCert and written in Coq.

high-performance RTL simulator

Project Oberon (New Edition 2013) Unofficial Mirror

Python Verilog value change dump (VCD) parser library + the nifty vcdcat VCD command line pretty printer.

RTL layout for Laravel Nova.

Display Django permissions in a HTML table that is translatable and easily customized.

NN on FPGA

RTL version of materializecss framework v1.0.0

🔧 Verilog plugin for Sublime Text 2/3. It helps to generate a simple testbench, instantiate a module, insert a user-header, repeat codes with formatted incremental/decremental numbers, etc.

👌🏼 CoreUI is free bootstrap admin template. http://coreui.io

WAL enables programmable waveform analysis.

Odoo (OpenERP) Right to left support for User Interface, report and frontend

HW Design: A Functional Approach

This ARMv4-compatible CPU core is written in synthesiable verilog.It could launch uCLinux and Linux in MODELSIM. It has high Dhrystone benchmark value: 1.2 DMIPS/MHz. It could be utilized in your FPGA design as one submodule, if you master the interface of this .v file. This IP core is very compact. It is one .v file and has only less 1800 lines.

An opinionated starter kit with styled-system, graphql-hooks, mobx and nextjs (PWA)

Landing page template built with one of most popular javascript library Vue.JS, Vuetify (Material Design) and Nuxt.JS with SSR.

PDP-6 Emulator

Simple way to set RTL for materializecss.com.

Upduino v2 with the ice40 up5k FPGA demos

Adds RTL support to Mattermost

List of ideas for getting started with TimVideos projects

A full-speed device-side USB peripheral core written in Verilog.

ARCHIVED - A Chrome extension to enable RTL support in https://notion.so

PCIe (1.0a to 2.0) Virtual host model for verilog

Generator of verilog description for FPGA MobileNet implementation

A collection of phase locked loop (PLL) related projects

Efficient implementations of the transcendental functions

ARV: Asynchronous RISC-V Go High-level Functional Model

An Verilog implementation of 7-to-1 LVDS Serializer. Which can be used for comunicating FPGAs with LVDS TFT Screens.

A simple Sphinx theme with RTL support.

OOUI is a modern JavaScript UI library with strong cross-browser support. It is the standard library for MediaWiki and Wikipedia. This is a mirror from https://gerrit.wikimedia.org. Main website:

Simple 3-stage pipeline RISC-V processor

MOS6581 SID chip emulator in SystemVerilog

Project X-Ray Database: XC7 Series

Leeneon is a free portfolio template designed and developed to be accessible for as many users as possible.

AXI support for Migen/MiSoC

FOSS Flow For FPGA

A FPGA implementation of the NTP and NTS protocols

This repository contains iCEBreaker examples for Amaranth HDL.

Fully pipelined Integer Scaled / Unscaled Radix-2 Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source language - VHDL / Verilog). GNU GPL 3.0.

Robotic Application Processor

FPGA core for SHA256d mining targeting Lattice iCE40 devices.

mirror of https://git.elphel.com/Elphel/eddr3

FAST-9 Accelerator for Corner Detection