841 Open source projects that are alternatives of or similar to virtio

Facilitates building open source tools for working with hardware description languages (HDLs)

Global Dark Mode for ALL apps on ANY platforms.

Sphinx Extension which generates various types of diagrams from Verilog code.

Tools for running FPGA vendor toolchains with Docker

VHDL/Verilog/SystemC code generator, simulator API written in python/c++

Fully pipelined Integer Scaled / Unscaled Radix-2 Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source language - VHDL / Verilog). GNU GPL 3.0.

FPGA-based RISC-V CPU+SoC.

A collection of phase locked loop (PLL) related projects

Hardware definition library and environment for designing and building digital hardware for FPGAs, using only open source tools

A hardware implementation of CNN, written by Verilog and synthesized on FPGA

Virtual development board for HDL design

Dockerfile with Vivado for CI

SpinalHDL - Cryptography libraries

Test suite designed to check compliance with the SystemVerilog standard.

FPGA-based USB-device controller to implement USB-CDC, USB-HID, etc.

Vivado and PetaLinux projects for Zynq EBAZ4205 Board

Recipe for FPGA cooking

Imitate SDcard using FPGAs.

Haskell library for hardware description

A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog

Various HDL (Verilog) IP Cores

A configurable C++ generator of pipelined Verilog FFT cores

Wishbone controlled I2C controllers

CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.

SHA-256 IP core for ZedBoard (Zynq SoC)

An FPGA implementation of a classic 80ies speech synthesizer. Done for the Retro Challenge 2017/10.

Video Game custom chips reverse-engineered from silicon

open-source IEEE 802.11 WiFi baseband FPGA (chip) design

DMA source and sink blocks for Xilinx Zynq FPGAs

Repository for basic (and not so basic) Verilog blocks with high re-use potential

Scala based HDL

Docker Development Environment for SpinalHDL

mirror of https://git.elphel.com/Elphel/eddr3

Cross EDA Abstraction and Automation

FPGA-based JPEG-LS image compressor.

Code generation tool for configuration and status registers

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

Show the time on a VGA monitor. Submitted for the Google MPW1 ASIC shuttle.

Example designs showing different ways to use SymbiFlow toolchains.

CAPCOM arcade hardware accurately replicated on MiST and MiSTer FPGA platforms. It covers Ghosts'n Goblins, 1942, 1943, Commando, F1-Dream, GunSmoke, Tiger Road, Black Tiger, Bionic Commando, Higemaru, Street Fighter and Vulgus.

The Antikernel operating system project

A reimplementation of a tiny stack CPU

OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/

Programmable multichannel ADPCM decoder for FPGA

A Video display simulator

Compact FPGA game console

A programming language for FPGAs.

High throughput JPEG decoder in Verilog for FPGA

SweRV EL2 Core

Materials for "Introduction to FPGA and Verilog" at MIPT DREC

i8080 precise replica in Verilog, based on reverse engineering of real die

Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation

Connectal is a framework for software-driven hardware development.

A utility for Composing FPGA designs from Peripherals

Tool to generate register RTL, models, and docs using SystemRDL or JSpec input

Verilog implementation of the symmetric block cipher AES (Advanced Encryption Standard) as specified in NIST FIPS 197. This implementation supports 128 and 256 bit keys.

DMA attacks over PCI Express based on Xilinx Zynq-7000 series SoC

LicheeTang 蜂鸟E203 Core

FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.

FPGA 101 - Workshop materials