808 Open source projects that are alternatives of or similar to Mips Cpu

RISC-V CPU Core (RV32IM)

A small, light weight, RISC CPU soft core

KianRISC-V! No RISC-V, no fun! RISC-V CPU with strong design rules and unittested! CPU you can trust! kianv rv32im risc-v a hdmi soc with harris computer architecture in verilog: multicycle, singlecycle and 5-stage pipelining Processor. Multicycle Soc with firmware that runs raytracer, mandelbrot, 3d hdmi gfx, dma controller, etc.....

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

NonTrivial-MIPS is a synthesizable superscalar MIPS processor with branch prediction and FPU support, and it is capable of booting linux.

A reimplementation of a tiny stack CPU

Human Resource Machine - CPU Design #HRM

32-bit Superscalar RISC-V CPU

A FPGA friendly 32 bit RISC-V CPU implementation

FPGA-based RISC-V CPU+SoC.

支持 45 条 MIPS 指令的单周期处理器 -- 计算机组成原理实验 NUAA Spring 2017

The Project TinyMIPS is dedicated to enabling undergraduates to build a complete computer system from scratch.

Haskell to VHDL/Verilog/SystemVerilog compiler

A FPGA implementation of the NTP and NTS protocols

❄️ Visual editor for open FPGA boards

Intermediate Representation Of Hardware Abstraction (LLVM-ish for HLS)

Fuxi (伏羲) is a 32-bit pipelined RISC-V processor written in Chisel3.

Wishbone controlled I2C controllers

FPGA core for SHA256d mining targeting Lattice iCE40 devices.

A bare bones, basic, ZipCPU system designed for both testing and quick integration into new systems

FPGA-based USB-device controller to implement USB-CDC, USB-HID, etc.

A collection of phase locked loop (PLL) related projects

Fully pipelined Integer Scaled / Unscaled Radix-2 Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source language - VHDL / Verilog). GNU GPL 3.0.

List of ideas for getting started with TimVideos projects

Video Game custom chips reverse-engineered from silicon

Haskell library for hardware description

A lightweight, open source and FPGA-friendly 32-bit CPU core based on an original instruction set

mirror of https://git.elphel.com/Elphel/eddr3

8051 soft CPU core. 700-lines statements for 111 instructions . Fully synthesizable Verilog-2001 core.

A full-speed device-side USB peripheral core written in Verilog.

FPGA-based Field Oriented Control (FOC) for driving BLDC/PMSM motor.

QNICE-FPGA is a 16-bit computer system for recreational programming built as a fully-fledged System-on-a-Chip in portable VHDL.

A configurable C++ generator of pipelined Verilog FFT cores

Useful m-scripts for DSP (CIC, FIR, FFT, Fast convolution, Partial Filters etc.)

Karuta HLS Compiler: High level synthesis from prototype based object oriented script language to RTL (Verilog) aiming to be useful for FPGA development.

Global Dark Mode for ALL apps on ANY platforms.

Minimal SDR with Lattice MachXO2 FPGA. And a port to Cyclone3 by Steven Groom

Robotic Application Processor

VHDL/Verilog/SystemC code generator, simulator API written in python/c++

An FPGA implementation of a classic 80ies speech synthesizer. Done for the Retro Challenge 2017/10.

Homebrew game for homebrew FPGA game console

Imitate SDcard using FPGAs.

A crazy small 8-bit CPU built with only seventeen 7400-series chips.

The OpenPiton Platform

🌟 IceZUM Alhambra: an Arduino-like Open FPGA electronic board

Repository for basic (and not so basic) Verilog blocks with high re-use potential

Simple, orthogonal 32-bit computer architecture and environment

KiwiSDR: BeagleBone web-accessible shortwave receiver and software-defined GPS

FPGA Haskell machine with game changing performance. Reduceron is Matthew Naylor, Colin Runciman and Jason Reich's high performance FPGA softcore for running lazy functional programs, including hardware garbage collection. Reduceron has been implemented on various FPGAs with clock frequency ranging from 60 to 150 MHz depending on the FPGA. A high degree of parallelism allows Reduceron to implement graph evaluation very efficiently. This fork aims to continue development on this, with a view to practical applications. Comments, questions, etc are welcome.

🌱 Open source ecosystem for open FPGA boards

A 32-bit RISC-V / MIPS ISA retargetable CPU core & SoC, 1.63 DMIPS/MHz

A Just-In-Time Compiler for Verilog from VMware Research

Various HDL (Verilog) IP Cores

An open source library for image processing on FPGA.

Unicorn CPU emulator framework (ARM, AArch64, M68K, Mips, Sparc, PowerPC, RiscV, X86)

Learn how to design digital systems and synthesize them into an FPGA using only opensource tools

The USRP™ Hardware Driver Repository

PlatformIO is a professional collaborative platform for embedded development 👽 A place where Developers and Teams have true Freedom! No more vendor lock-in!

Scala based HDL

PlatformIO IDE for Atom: The next generation integrated development environment for IoT