Skywater PdkOpen source process design kit for usage with SkyWater Technology Foundry's 130nm node.
Stars: ✭ 1,765 (+222.08%)
caravel mpw-oneCaravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.
Stars: ✭ 130 (-76.28%)
OpenlaneOpenLANE is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, Fault and custom methodology scripts for design exploration and optimization.
Stars: ✭ 293 (-46.53%)
CoresVarious HDL (Verilog) IP Cores
Stars: ✭ 271 (-50.55%)
LogicCMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.
Stars: ✭ 149 (-72.81%)
padringA padring generator for ASICs
Stars: ✭ 19 (-96.53%)
RggenCode generation tool for configuration and status registers
Stars: ✭ 54 (-90.15%)
OpenROAD-flow-scriptsOpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/
Stars: ✭ 124 (-77.37%)
LivehdLive Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation
Stars: ✭ 110 (-79.93%)
dockerScripts to build and use docker images including GHDL
Stars: ✭ 27 (-95.07%)
FPGA-USB-DeviceFPGA-based USB-device controller to implement USB-CDC, USB-HID, etc.
Stars: ✭ 29 (-94.71%)
SpinalhdlScala based HDL
Stars: ✭ 696 (+27.01%)
AtalantaAtalanta is a modified ATPG (Automatic Test Pattern Generation) tool and fault simulator, orginally from VirginiaTech University.
Stars: ✭ 49 (-91.06%)
hwtVHDL/Verilog/SystemC code generator, simulator API written in python/c++
Stars: ✭ 145 (-73.54%)
OpenroadOpenROAD's unified application implementing an RTL-to-GDS Flow
Stars: ✭ 270 (-50.73%)
VerilogRepository for basic (and not so basic) Verilog blocks with high re-use potential
Stars: ✭ 296 (-45.99%)
ofdmChisel Things for OFDM
Stars: ✭ 23 (-95.8%)
Chisel3Chisel 3: A Modern Hardware Design Language
Stars: ✭ 2,290 (+317.88%)
Darkriscvopensouce RISC-V cpu core implemented in Verilog from scratch in one night!
Stars: ✭ 1,062 (+93.8%)
VGChipsVideo Game custom chips reverse-engineered from silicon
Stars: ✭ 86 (-84.31%)
AesVerilog implementation of the symmetric block cipher AES (Advanced Encryption Standard) as specified in NIST FIPS 197. This implementation supports 128 and 256 bit keys.
Stars: ✭ 131 (-76.09%)
Biriscv32-bit Superscalar RISC-V CPU
Stars: ✭ 208 (-62.04%)
AxiAXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
Stars: ✭ 227 (-58.58%)
DFFRAMStandard Cell Library based Memory Compiler using FF/Latch cells
Stars: ✭ 54 (-90.15%)
Clash CompilerHaskell to VHDL/Verilog/SystemVerilog compiler
Stars: ✭ 958 (+74.82%)
SpinalDevDocker Development Environment for SpinalHDL
Stars: ✭ 17 (-96.9%)
formal hw verificationTrying to verify Verilog/VHDL designs with formal methods and tools
Stars: ✭ 32 (-94.16%)
virtioVirtio implementation in SystemVerilog
Stars: ✭ 38 (-93.07%)
cnn openA hardware implementation of CNN, written by Verilog and synthesized on FPGA
Stars: ✭ 157 (-71.35%)
Open Register Design ToolTool to generate register RTL, models, and docs using SystemRDL or JSpec input
Stars: ✭ 126 (-77.01%)
hdl-toolsFacilitates building open source tools for working with hardware description languages (HDLs)
Stars: ✭ 56 (-89.78%)
spu32Small Processing Unit 32: A compact RV32I CPU written in Verilog
Stars: ✭ 51 (-90.69%)
Fake-SDcardImitate SDcard using FPGAs.
Stars: ✭ 26 (-95.26%)
sv-testsTest suite designed to check compliance with the SystemVerilog standard.
Stars: ✭ 148 (-72.99%)
Scr1SCR1 is a high-quality open-source RISC-V MCU core in Verilog
Stars: ✭ 393 (-28.28%)
blarneyHaskell library for hardware description
Stars: ✭ 81 (-85.22%)
Sv TestsTest suite designed to check compliance with the SystemVerilog standard.
Stars: ✭ 108 (-80.29%)
Ustc RvsocFPGA-based RISC-V CPU+SoC.
Stars: ✭ 77 (-85.95%)
RiscvRISC-V CPU Core (RV32IM)
Stars: ✭ 272 (-50.36%)
vga-clockShow the time on a VGA monitor. Submitted for the Google MPW1 ASIC shuttle.
Stars: ✭ 48 (-91.24%)
SpinalCryptoSpinalHDL - Cryptography libraries
Stars: ✭ 36 (-93.43%)
Hard-JPEG-LSFPGA-based JPEG-LS image compressor.
Stars: ✭ 52 (-90.51%)
pygearsHW Design: A Functional Approach
Stars: ✭ 122 (-77.74%)
FpOCFPGA-based Field Oriented Control (FOC) for driving BLDC/PMSM motor.
Stars: ✭ 138 (-74.82%)
karutaKaruta HLS Compiler: High level synthesis from prototype based object oriented script language to RTL (Verilog) aiming to be useful for FPGA development.
Stars: ✭ 89 (-83.76%)
jekyll-theme-mehdix-rtlA right-to-left theme for Jekyll with Jalali support and some other goodies.
Stars: ✭ 38 (-93.07%)
cocotb-busPre-packaged testbenching tools and reusable bus interfaces for cocotb
Stars: ✭ 20 (-96.35%)
verismithVerilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.
Stars: ✭ 74 (-86.5%)
enlite-starterEnlite Starter - React Dashboard Starter Template with Firebase Auth
Stars: ✭ 28 (-94.89%)
dblclockfftA configurable C++ generator of pipelined Verilog FFT cores
Stars: ✭ 147 (-73.18%)
uiAdd right-to-left support to the NativeScript framework
Stars: ✭ 22 (-95.99%)
nim magicNim cell magic for JupyterLab or Juypter Python Notebooks.
Stars: ✭ 41 (-92.52%)
ser334-publicThis repository contains public source files for use in SER334 (Operating Systems & Networks) at Arizona State University.
Stars: ✭ 28 (-94.89%)