989 Open source projects that are alternatives of or similar to Riscv

32-bit Superscalar RISC-V CPU

FPGA-based RISC-V CPU+SoC.

CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

A small, light weight, RISC CPU soft core

A small and customizable full-scale 32-bit RISC-V soft-core CPU and SoC written in platform-independent VHDL.

Yet Another RISC-V Implementation

Verilog implementation of the symmetric block cipher AES (Advanced Encryption Standard) as specified in NIST FIPS 197. This implementation supports 128 and 256 bit keys.

A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog

RISC-V Cores, SoC platforms and SoCs

Homebrew game for homebrew FPGA game console

Various HDL (Verilog) IP Cores

Code generation tool for configuration and status registers

Human Resource Machine - CPU Design #HRM

Video Game custom chips reverse-engineered from silicon

Portable games console, designed from scratch: CPU, graphics, PCB, and the kitchen sink

LicheeTang 蜂鸟E203 Core

VUnit is a unit testing framework for VHDL/SystemVerilog

Compact FPGA game console

List of ideas for getting started with TimVideos projects

Haskell to VHDL/Verilog/SystemVerilog compiler

A MIPS CPU implemented in Verilog

A reimplementation of a tiny stack CPU

A FPGA friendly 32 bit RISC-V CPU implementation

This repository hosts the project for open-source hummingbird E203 RISC processor Core.

Tool to generate register RTL, models, and docs using SystemRDL or JSpec input

KianRISC-V! No RISC-V, no fun! RISC-V CPU with strong design rules and unittested! CPU you can trust! kianv rv32im risc-v a hdmi soc with harris computer architecture in verilog: multicycle, singlecycle and 5-stage pipelining Processor. Multicycle Soc with firmware that runs raytracer, mandelbrot, 3d hdmi gfx, dma controller, etc.....

PlatformIO is a professional collaborative platform for embedded development 👽 A place where Developers and Teams have true Freedom! No more vendor lock-in!

RISC-V Cores, SoC platforms and SoCs

The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation

Materials for "Introduction to FPGA and Verilog" at MIPT DREC

Small Processing Unit 32: A compact RV32I CPU written in Verilog

The Project TinyMIPS is dedicated to enabling undergraduates to build a complete computer system from scratch.

FPGA-based JPEG-LS image compressor.

PDP-6 Emulator

This ARMv4-compatible CPU core is written in synthesiable verilog.It could launch uCLinux and Linux in MODELSIM. It has high Dhrystone benchmark value: 1.2 DMIPS/MHz. It could be utilized in your FPGA design as one submodule, if you master the interface of this .v file. This IP core is very compact. It is one .v file and has only less 1800 lines.

SpinalHDL - Cryptography libraries

ROS 2 Hardware Acceleration Working Group community governance model & list of projects

RISC-V processor emulator written in Rust+WASM

NN on FPGA

A formally verified high-level synthesis tool based on CompCert and written in Coq.

Fork of OpenVeriFla - FPGA debugging logic analyzer to use with your designs - examples (so far) for ice40/IceStorm

Generator of verilog description for FPGA MobileNet implementation

Yet another toy CPU.

Pipelined implementation of Sobel Edge Detection on OV7670 camera and on still images

Imitate SDcard using FPGAs.

NVDLA (An Opensource DL Accelerator Framework) implementation on FPGA.

FPGA Verilog implementation of 1949 EDSAC Computer with animated tape reader, panel, teleprinter and CRT scope

A crazy small 8-bit CPU built with only seventeen 7400-series chips.

FPGA-based Field Oriented Control (FOC) for driving BLDC/PMSM motor.

Import and export IP-XACT XML register models

Karuta HLS Compiler: High level synthesis from prototype based object oriented script language to RTL (Verilog) aiming to be useful for FPGA development.

8051 soft CPU core. 700-lines statements for 111 instructions . Fully synthesizable Verilog-2001 core.

A FPGA implementation of the NTP and NTS protocols

Fully pipelined Integer Scaled / Unscaled Radix-2 Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source language - VHDL / Verilog). GNU GPL 3.0.

The Simple 5-staged pipeline RISC-V written in chisel3 for intel FPGA.

mirror of https://git.elphel.com/Elphel/eddr3

Haskell library for hardware description

An FPGA implementation of a classic 80ies speech synthesizer. Done for the Retro Challenge 2017/10.