OpenLANE is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, Fault and custom methodology scripts for design exploration and optimization.

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Hardware definition library and environment for designing and building digital hardware for FPGAs, using only open source tools

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PyChip-py-hcl

A Hardware Construct Language

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Test suite designed to check compliance with the SystemVerilog standard.

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Chisel3

Chisel 3: A Modern Hardware Design Language

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A hardware implementation of CNN, written by Verilog and synthesized on FPGA

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SpinalDev

Docker Development Environment for SpinalHDL

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SpinalCrypto

SpinalHDL - Cryptography libraries

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vboard

Virtual development board for HDL design

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FPGA-based JPEG-LS image compressor.

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Openroad

OpenROAD's unified application implementing an RTL-to-GDS Flow

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Scala based HDL

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OpenLane

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, Fault and custom methodology scripts for design exploration and optimization.

Stars: ✭ 548 (+270.27%)

Mutual labels: rtl, verilog

Rggen

Code generation tool for configuration and status registers

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Mutual labels: rtl, verilog

Ustc Rvsoc

FPGA-based RISC-V CPU+SoC.

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xeda

Cross EDA Abstraction and Automation

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Mutual labels: verilog, hdl

Scr1

SCR1 is a high-quality open-source RISC-V MCU core in Verilog

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Mutual labels: rtl, verilog

blarney

Haskell library for hardware description

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cpu11

Revengineered ancient PDP-11 CPUs, originals and clones

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ACT hardware description language and core tools.

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react-gallery-carousel

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Global Dark Mode for ALL apps on ANY platforms.

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mkdocs rtl theme based on mkdocs-material

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ruby-vpi

Ruby interface to IEEE 1364-2005 Verilog VPI

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32-Verilog-Mini-Projects

Implementing 32 Verilog Mini Projects. 32 bit adder, Array Multiplier, Barrel Shifter, Binary Divider 16 by 8, Booth Multiplication, CRC Coding, Carry Select and Carry Look Ahead Adder, Carry Skip and Carry Save Adder, Complex Multiplier, Dice Game, FIFO, Fixed Point Adder and Subtractor, Fixed Point Multiplier and Divider, Floating Point IEEE 7…

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Scripts to build and use docker images including GHDL

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honeywell-wireless-doorbell

Understanding the RF signal used in the Honeywell RCWL300A, RCWL330A, Series 3, 5, 9 and Decor Series Wireless Chimes

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postcss-bidirection

PostCSS plugin that polyfill Bi-directional CSS properties and values to suppot rtl and ltr rules in all browsers