426 Open source projects that are alternatives of or similar to riscv-cores-list

RISC-V CPU Core (RV32IM)

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Video Game custom chips reverse-engineered from silicon

Haskell to VHDL/Verilog/SystemVerilog compiler

SweRV EH1 core

A simple three-stage RISC-V CPU

FPGA-based RISC-V CPU+SoC.

Compact FPGA game console

FPGA CryptoNight V7 Minner

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Code generation tool for configuration and status registers

A small and customizable full-scale 32-bit RISC-V soft-core CPU and SoC written in platform-independent VHDL.

The Simple 5-staged pipeline RISC-V written in chisel3 for intel FPGA.

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opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

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AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.

32-bit RISC-V system on chip for iCE40 and ECP5 FPGAs

Import and export IP-XACT XML register models

collection of works aiming at reducing model sizes or the ASIC/FPGA accelerator for machine learning

The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

Tool to generate register RTL, models, and docs using SystemRDL or JSpec input

720p FPGA Media Player (RISC-V + Motion JPEG + SD + HDMI on an Artix 7)

Verilog implementation of the symmetric block cipher AES (Advanced Encryption Standard) as specified in NIST FIPS 197. This implementation supports 128 and 256 bit keys.

SweRV EL2 Core

Yet Another RISC-V Implementation

Small Processing Unit 32: A compact RV32I CPU written in Verilog

Homebrew game for homebrew FPGA game console

Software, tools, and documentation for RV32-VEGA-Lite platform

PlatformIO is a professional collaborative platform for embedded development 👽 A place where Developers and Teams have true Freedom! No more vendor lock-in!

Portable games console, designed from scratch: CPU, graphics, PCB, and the kitchen sink

Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation

SystemRDL 2.0 language compiler front-end

No-MMU Linux capable RISC-V SoC designed to be useful.

Polyphony is Python based High-Level Synthesis compiler.

Tiny RISC-V virtual machine

Small-scale Tensor Processing Unit built on an FPGA

VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!

Mining Pools Made Easy. ⛏ 📦 🏆

Programmable multichannel ADPCM decoder for FPGA

🎯 soap - Structural Optimisation of Arithmetic Programs

hBPF = eBPF in hardware

A padring generator for ASICs

A hardware implementation of CNN, written by Verilog and synthesized on FPGA

Functional verification project for the CORE-V family of RISC-V cores.

A programming language for FPGAs.

A port of FreeRTOS for the RISC-V ISA

Universal Cooperative Multithread Lib with real time Scheduler that was designed to work, virtually, into any modern micro controller or Microchip and, also, for user space applications for modern OS (Mac, Linux, Windows) or on FreeRTOS as well. Supports C and C++

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Show the time on a VGA monitor. Submitted for the Google MPW1 ASIC shuttle.