695 Open source projects that are alternatives of or similar to Rggen

Various HDL (Verilog) IP Cores

CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.

Tool to generate register RTL, models, and docs using SystemRDL or JSpec input

VHDL/Verilog/SystemC code generator, simulator API written in python/c++

Virtio implementation in SystemVerilog

FPGA-based RISC-V CPU+SoC.

SystemRDL 2.0 language compiler front-end

An abstraction library for interfacing EDA tools

OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

Repository for basic (and not so basic) Verilog blocks with high re-use potential

Imitate SDcard using FPGAs.

RISC-V CPU Core (RV32IM)

Haskell to VHDL/Verilog/SystemVerilog compiler

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

Recipe for FPGA cooking

A hardware implementation of CNN, written by Verilog and synthesized on FPGA

OpenROAD's unified application implementing an RTL-to-GDS Flow

Docker Development Environment for SpinalHDL

OpenLANE is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, Fault and custom methodology scripts for design exploration and optimization.

Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation

Verilog implementation of the symmetric block cipher AES (Advanced Encryption Standard) as specified in NIST FIPS 197. This implementation supports 128 and 256 bit keys.

Verilog to Routing -- Open Source CAD Flow for FPGA Research

Show the time on a VGA monitor. Submitted for the Google MPW1 ASIC shuttle.

Sphinx Extension which generates various types of diagrams from Verilog code.

SpinalHDL - Cryptography libraries

FPGA-based JPEG-LS image compressor.

FPGA-based USB-device controller to implement USB-CDC, USB-HID, etc.

32-bit Superscalar RISC-V CPU

Haskell library for hardware description

Video Game custom chips reverse-engineered from silicon

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, Fault and custom methodology scripts for design exploration and optimization.

Scala based HDL

Cross EDA Abstraction and Automation

Import and export IP-XACT XML register models

Generate UVM register model from compiled SystemRDL input

Global Dark Mode for ALL apps on ANY platforms.

🤖 SoCFPGA: Open Source embedded Linux developed for Intel (ALTERA) SoC-FPGAs (Cyclone V & Arria 10)

Ophidian's Mirror Repository on github. https://gitlab.com/eclufsc/eda/ophidian

Minimal SDR with Lattice MachXO2 FPGA. And a port to Cyclone3 by Steven Groom

DFiant: A Dataflow Hardware Descripition Language

Robotic Application Processor

Image Processing Toolbox in Verilog using Basys3 FPGA

❄️ Visual editor for open FPGA boards

A collection of phase locked loop (PLL) related projects

Homebrew game for homebrew FPGA game console

Intermediate Representation Of Hardware Abstraction (LLVM-ish for HLS)

Chisel Things for OFDM

Test suite designed to check compliance with the SystemVerilog standard.

Fully pipelined Integer Scaled / Unscaled Radix-2 Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source language - VHDL / Verilog). GNU GPL 3.0.

A bare bones, basic, ZipCPU system designed for both testing and quick integration into new systems

🌟 IceZUM Alhambra: an Arduino-like Open FPGA electronic board

FPGA CryptoNight V7 Minner

An FPGA implementation of a classic 80ies speech synthesizer. Done for the Retro Challenge 2017/10.

A wishbone controlled scope for FPGA's

A MIPS CPU implemented in Verilog

FPGA Haskell machine with game changing performance. Reduceron is Matthew Naylor, Colin Runciman and Jason Reich's high performance FPGA softcore for running lazy functional programs, including hardware garbage collection. Reduceron has been implemented on various FPGAs with clock frequency ranging from 60 to 150 MHz depending on the FPGA. A high degree of parallelism allows Reduceron to implement graph evaluation very efficiently. This fork aims to continue development on this, with a view to practical applications. Comments, questions, etc are welcome.

KiwiSDR: BeagleBone web-accessible shortwave receiver and software-defined GPS

An open source library for image processing on FPGA.

SCR1 is a high-quality open-source RISC-V MCU core in Verilog