Top 342 verilog open source projects

🔧 Verilog plugin for Sublime Text 2/3. It helps to generate a simple testbench, instantiate a module, insert a user-header, repeat codes with formatted incremental/decremental numbers, etc.

✭ 25

python Verilog sublime-text verilog verilog-gadget

ARM9-compatible-soft-CPU-core

This ARMv4-compatible CPU core is written in synthesiable verilog.It could launch uCLinux and Linux in MODELSIM. It has high Dhrystone benchmark value: 1.2 DMIPS/MHz. It could be utilized in your FPGA design as one submodule, if you master the interface of this .v file. This IP core is very compact. It is one .v file and has only less 1800 lines.

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Verilog HTML CSS cpu verilog 32-bit armv4

pdp6

PDP-6 Emulator

✭ 47

c Verilog SourcePawn pascal assembly Makefile fpga simulation emulation verilog retrocomputing computer-history pdp-6

Hard-JPEG-LS

FPGA-based JPEG-LS image compressor.

✭ 52

SystemVerilog Batchfile fpga rtl verilog jpeg-ls jpegls jls

vboard

Virtual development board for HDL design

✭ 32

VHDL python c Makefile shell vhdl verilog hdl ghdl cosim vpi verilator fli vhpidirect

SpinalCrypto

SpinalHDL - Cryptography libraries

✭ 36

scala java cryptography crypto fpga aes vhdl md5 sha rtl verilog crc hmac des spinalhdl

MobileNet-in-FPGA

Generator of verilog description for FPGA MobileNet implementation

✭ 107

Verilog python shell tcl fpga verilog fpga-mobilenet

async fifo

A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog

✭ 117

Verilog SystemVerilog fpga verification verilog synthesis icarus-verilog fifo hdl verilog-hdl fifo-queue fifo-cache

LVDS-7-to-1-Serializer

An Verilog implementation of 7-to-1 LVDS Serializer. Which can be used for comunicating FPGAs with LVDS TFT Screens.

✭ 33

Verilog fpga lcd serializer verilog screens lvds

srv32

Simple 3-stage pipeline RISC-V processor

✭ 88

c Verilog Makefile SystemVerilog assembly C++verilog risc-v rv32im

verilog-sid-mos6581

MOS6581 SID chip emulator in SystemVerilog

✭ 22

SystemVerilog fpga c64 verilog chiptune sid sound-synthesis 6581 8580

FAST9-Accelerator

FAST-9 Accelerator for Corner Detection

✭ 32

Verilog C++opencv algorithm accelerator image-processing verilog corner-detection

sphinxcontrib-hdl-diagrams

Sphinx Extension which generates various types of diagrams from Verilog code.

✭ 37

python Makefile Verilog documentation fpga sphinx documentation-tool rtl verilog diagrams hdl yosys sphinx-extension symbiflow

Solutions-to-HDLbits-Verilog-sets

Here are my solutions to HDLbits Verilog problem sets (HDLbits: https://hdlbits.01xz.net/wiki/Main_Page).

✭ 57

Verilog V verilog hdlbits

spu32

Small Processing Unit 32: A compact RV32I CPU written in Verilog

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c Verilog Makefile assembly fpga verilog icestorm risc-v ice40 rv32i system-on-chip risc-processor

virtio

Virtio implementation in SystemVerilog

✭ 38

SystemVerilog CMake python Vim Script cmake fpga model rtl verilog xilinx vivado systemc hdl virtio verilator quartus

hdl-tools

Facilitates building open source tools for working with hardware description languages (HDLs)

✭ 56

perl tcl Makefile shell rtl verilog gtkwave hdl verilator

PyChip-py-hcl

A Hardware Construct Language

✭ 36

python C++rtl firrtl verilog hardware-designs

OpenROAD-flow-scripts

OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/

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Verilog SourcePawn tcl python Makefile shell eda rtl verilog def gdsii timing-analysis openroad lef opendb-database

gateware-ts

Hardware definition library and environment for designing and building digital hardware for FPGAs, using only open source tools

✭ 83

typescript javascript fpga hardware simulation verilog hdl gateware

cnn open

A hardware implementation of CNN, written by Verilog and synthesized on FPGA

✭ 157

Coq Verilog Jupyter Notebook VHDL tcl shell fpga cnn rtl verilog lenet

platform-lattice ice40

Lattice iCE40: development platform for PlatformIO

✭ 34

python fpga platformio verilog icestorm lattice platformio-platform

drec-fpga-intro

Materials for "Introduction to FPGA and Verilog" at MIPT DREC

✭ 66

Verilog Makefile assembly c education fpga verilog risc-v

verilog-vcd-parser

A parser for Value Change Dump (VCD) files as specified in the IEEE System Verilog 1800-2012 standard.

✭ 46

C++Lex Makefile parser simulation vhdl trace verilog vcd

ics-adpcm

Programmable multichannel ADPCM decoder for FPGA

✭ 18

Verilog shell audio fpga verilog adpcm

yahdl

A programming language for FPGAs.

✭ 20

java ANTLR fpga transpiler verilog antlr4

xeda

Cross EDA Abstraction and Automation

✭ 25

python tcl automation fpga hardware simulation vhdl eda verilog synthesis hdl

yafpgatetris

Yet Another Tetris on FPGA Implementation

✭ 29

Verilog SystemVerilog tcl shell python fpga tetris verilog de1-soc fpga-game

FPGA ThreeLevelStorage

【原创，已被编入官方教材】Three-level storage subsystem(SD+DDR2 SDRAM+Cache), based on Nexys4 FPGA board. 同济大学计算机系统结构课程设计，FPGA三级存储子系统。

✭ 86

Coq VHDL Verilog c SystemVerilog shell fpga ddr verilog sd-card sdram-controller

Atalanta

Atalanta is a modified ATPG (Automatic Test Pattern Generation) tool and fault simulator, orginally from VirginiaTech University.

✭ 49

Verilog C++Coq verilog vlsi atalanta atpg

svut

SVUT is a simple framework to create Verilog/SystemVerilog unit tests. Just focus on your tests!

✭ 48

python SystemVerilog shell Verilog C++simulator tdd simulation foss verilog testcase tdd-utilities mit-license icarus-verilog gtkwave verification-methodologies vcd verilator svut

vscode-terosHDL

VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!

✭ 325

javascript typescript HTML CSS python shell fpga vhdl verilog

TinyGarble

TinyGarble: Logic Synthesis and Sequential Descriptions for Yao's Garbled Circuits

✭ 108

C++c CMake Makefile security-protocol verilog garbled-circuits circuit-description

vga-clock

Show the time on a VGA monitor. Submitted for the Google MPW1 ASIC shuttle.

✭ 48

Verilog fpga simulation rtl verilog

tree-core-ide

The next generation integrated development environment for processor design and verification. It has multi-hardware language support, open source IP management and easy-to-use rtl simulation toolset.

✭ 79

javascript Vue HTML webgl processor ide waveform riscv chisel3 verilog vscode-extension simualtion

kianRiscV

KianRISC-V! No RISC-V, no fun! RISC-V CPU with strong design rules and unittested! CPU you can trust! kianv rv32im risc-v a hdmi soc with harris computer architecture in verilog: multicycle, singlecycle and 5-stage pipelining Processor. Multicycle Soc with firmware that runs raytracer, mandelbrot, 3d hdmi gfx, dma controller, etc.....

✭ 167

AGS Script assembly c Verilog tcl SystemVerilog cpu fpga riscv verilog breakout divider ice40 ds3231 multiplier icoboard icebreaker pipelined ecp5 rv32im ice40hx1k ulx3s icefun softcpu sd1306 sd1331

picorv32 Xilinx

A picorv32-riscv Soc with DMAC and Ethernet controller & lwip & Kirtex7@333MHz

✭ 49

Verilog c Makefile C++tcl CMake verilog risc-v

my hdmi device

New clean hdmi implementation for ulx3s, icestick, icoboard, arty7, colorlight i5 and blackicemx! With tmds encoding hacked down from dvi standard. Supports DDR and SRD tranfser!

✭ 66