All Projects → Vunit → Similar Projects or Alternatives

908 Open source projects that are alternatives of or similar to Vunit

Logic
CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.
Stars: ✭ 149 (-65.98%)
Mutual labels:  fpga, asic, verification
Clash Compiler
Haskell to VHDL/Verilog/SystemVerilog compiler
Stars: ✭ 958 (+118.72%)
Mutual labels:  fpga, vhdl, asic
Riscv
RISC-V CPU Core (RV32IM)
Stars: ✭ 272 (-37.9%)
Mutual labels:  fpga, asic, verification
Aes
Verilog implementation of the symmetric block cipher AES (Advanced Encryption Standard) as specified in NIST FIPS 197. This implementation supports 128 and 256 bit keys.
Stars: ✭ 131 (-70.09%)
Mutual labels:  fpga, asic
Cva6
The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
Stars: ✭ 1,144 (+161.19%)
Mutual labels:  fpga, asic
Neo430
A very small msp430-compatible customizable soft-core microcontroller-like processor system written in platform-independent VHDL.
Stars: ✭ 120 (-72.6%)
Mutual labels:  fpga, vhdl
fpga-docker
Tools for running FPGA vendor toolchains with Docker
Stars: ✭ 54 (-87.67%)
Mutual labels:  fpga, vhdl
Forth Cpu
A Forth CPU and System on a Chip, based on the J1, written in VHDL
Stars: ✭ 244 (-44.29%)
Mutual labels:  fpga, vhdl
fpga torture
🔥 Technology-agnostic FPGA stress-test: maximum logic utilization and high dynamic power consumption.
Stars: ✭ 23 (-94.75%)
Mutual labels:  fpga, vhdl
xeda
Cross EDA Abstraction and Automation
Stars: ✭ 25 (-94.29%)
Mutual labels:  fpga, vhdl
pygears
HW Design: A Functional Approach
Stars: ✭ 122 (-72.15%)
Mutual labels:  asic, fpga
Rggen
Code generation tool for configuration and status registers
Stars: ✭ 54 (-87.67%)
Mutual labels:  fpga, asic
Haddoc2
Caffe to VHDL
Stars: ✭ 57 (-86.99%)
Mutual labels:  fpga, vhdl
Livehd
Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation
Stars: ✭ 110 (-74.89%)
Mutual labels:  fpga, asic
Simon speck ciphers
Implementations of the Simon and Speck Block Ciphers
Stars: ✭ 74 (-83.11%)
Mutual labels:  fpga, vhdl
Biriscv
32-bit Superscalar RISC-V CPU
Stars: ✭ 208 (-52.51%)
Mutual labels:  fpga, asic
Axi
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
Stars: ✭ 227 (-48.17%)
Mutual labels:  fpga, asic
vscode-terosHDL
VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!
Stars: ✭ 325 (-25.8%)
Mutual labels:  fpga, vhdl
Space Invaders Vhdl
Space Invaders game implemented with VHDL
Stars: ✭ 142 (-67.58%)
Mutual labels:  fpga, vhdl
PeakRDL-ipxact
Import and export IP-XACT XML register models
Stars: ✭ 21 (-95.21%)
Mutual labels:  asic, fpga
noasic
An open-source VHDL library for FPGA design.
Stars: ✭ 27 (-93.84%)
Mutual labels:  fpga, vhdl
fphdl
VHDL-2008 Support Library
Stars: ✭ 36 (-91.78%)
Mutual labels:  vhdl, verification
math
Useful m-scripts for DSP (CIC, FIR, FFT, Fast convolution, Partial Filters etc.)
Stars: ✭ 15 (-96.58%)
Mutual labels:  fpga, vhdl
getting-started
List of ideas for getting started with TimVideos projects
Stars: ✭ 50 (-88.58%)
Mutual labels:  fpga, vhdl
FPGA CryptoNight V7
FPGA CryptoNight V7 Minner
Stars: ✭ 21 (-95.21%)
Mutual labels:  asic, fpga
intfftk
Fully pipelined Integer Scaled / Unscaled Radix-2 Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source language - VHDL / Verilog). GNU GPL 3.0.
Stars: ✭ 43 (-90.18%)
Mutual labels:  fpga, vhdl
Spi Fpga
SPI master and slave for FPGA written in VHDL
Stars: ✭ 50 (-88.58%)
Mutual labels:  fpga, vhdl
Vexriscv
A FPGA friendly 32 bit RISC-V CPU implementation
Stars: ✭ 1,041 (+137.67%)
Mutual labels:  fpga, vhdl
J1sc
A reimplementation of a tiny stack CPU
Stars: ✭ 64 (-85.39%)
Mutual labels:  fpga, vhdl
Fpga Fft
A highly optimized streaming FFT core based on Bailey's 4-step large FFT algorithm
Stars: ✭ 45 (-89.73%)
Mutual labels:  fpga, vhdl
Neorv32
A small and customizable full-scale 32-bit RISC-V soft-core CPU and SoC written in platform-independent VHDL.
Stars: ✭ 106 (-75.8%)
Mutual labels:  fpga, vhdl
Systemrdl Compiler
SystemRDL 2.0 language compiler front-end
Stars: ✭ 95 (-78.31%)
Mutual labels:  fpga, asic
Open Register Design Tool
Tool to generate register RTL, models, and docs using SystemRDL or JSpec input
Stars: ✭ 126 (-71.23%)
Mutual labels:  fpga, asic
Image Processing
Image Processing Toolbox in Verilog using Basys3 FPGA
Stars: ✭ 31 (-92.92%)
Mutual labels:  fpga, vhdl
Tinytpu
Implementation of a Tensor Processing Unit for embedded systems and the IoT.
Stars: ✭ 153 (-65.07%)
Mutual labels:  fpga, vhdl
simple-riscv
A simple three-stage RISC-V CPU
Stars: ✭ 14 (-96.8%)
Mutual labels:  fpga, vhdl
Edalize
An abstraction library for interfacing EDA tools
Stars: ✭ 270 (-38.36%)
Mutual labels:  fpga, vhdl
F32c
A 32-bit RISC-V / MIPS ISA retargetable CPU core & SoC, 1.63 DMIPS/MHz
Stars: ✭ 338 (-22.83%)
Mutual labels:  fpga, vhdl
Fletcher
Fletcher: A framework to integrate FPGA accelerators with Apache Arrow
Stars: ✭ 144 (-67.12%)
Mutual labels:  fpga, vhdl
awesome-hwd-tools
A curated list of awesome open source hardware design tools
Stars: ✭ 42 (-90.41%)
Mutual labels:  asic, fpga
SpinalDev
Docker Development Environment for SpinalHDL
Stars: ✭ 17 (-96.12%)
Mutual labels:  fpga, vhdl
captouch
👇 Add capacitive touch buttons to any FPGA!
Stars: ✭ 96 (-78.08%)
Mutual labels:  fpga, vhdl
SpinalCrypto
SpinalHDL - Cryptography libraries
Stars: ✭ 36 (-91.78%)
Mutual labels:  fpga, vhdl
async fifo
A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
Stars: ✭ 117 (-73.29%)
Mutual labels:  fpga, verification
JSON-for-VHDL
A JSON library implemented in VHDL.
Stars: ✭ 56 (-87.21%)
Mutual labels:  fpga, vhdl
vhdl-hdmi-out
HDMI Out VHDL code for 7-series Xilinx FPGAs
Stars: ✭ 36 (-91.78%)
Mutual labels:  fpga, vhdl
QNICE-FPGA
QNICE-FPGA is a 16-bit computer system for recreational programming built as a fully-fledged System-on-a-Chip in portable VHDL.
Stars: ✭ 51 (-88.36%)
Mutual labels:  fpga, vhdl
PoC-Examples
This repository contains synthesizable examples which use the PoC-Library.
Stars: ✭ 27 (-93.84%)
Mutual labels:  fpga, vhdl
PeakRDL-uvm
Generate UVM register model from compiled SystemRDL input
Stars: ✭ 25 (-94.29%)
Mutual labels:  asic, fpga
BenEaterVHDL
VHDL project to run a simple 8-bit computer very similar to the one built by Ben Eater (see https://eater.net)
Stars: ✭ 30 (-93.15%)
Mutual labels:  fpga, vhdl
fpga puf
🔑 Technology-agnostic Physical Unclonable Function (PUF) hardware module for any FPGA.
Stars: ✭ 44 (-89.95%)
Mutual labels:  fpga, vhdl
VGChips
Video Game custom chips reverse-engineered from silicon
Stars: ✭ 86 (-80.37%)
Mutual labels:  asic, fpga
awesome-dv
Awesome ASIC design verification
Stars: ✭ 76 (-82.65%)
Mutual labels:  asic, verification
DFiant
DFiant: A Dataflow Hardware Descripition Language
Stars: ✭ 21 (-95.21%)
Mutual labels:  asic, fpga
Aes
AES-128 hardware implementation
Stars: ✭ 25 (-94.29%)
Mutual labels:  fpga, vhdl
Lxp32 Cpu
A lightweight, open source and FPGA-friendly 32-bit CPU core based on an original instruction set
Stars: ✭ 27 (-93.84%)
Mutual labels:  fpga, vhdl
riscv-cores-list
RISC-V Cores, SoC platforms and SoCs
Stars: ✭ 651 (+48.63%)
Mutual labels:  asic, fpga
hwt
VHDL/Verilog/SystemC code generator, simulator API written in python/c++
Stars: ✭ 145 (-66.89%)
Mutual labels:  fpga, vhdl
Cores
Various HDL (Verilog) IP Cores
Stars: ✭ 271 (-38.13%)
Mutual labels:  fpga, asic
Hal
HAL – The Hardware Analyzer
Stars: ✭ 298 (-31.96%)
Mutual labels:  fpga, vhdl
1-60 of 908 similar projects