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Top 342 verilog open source projects

Verilog Pcie

Verilog PCI express components

✭ 252

verilog

Fake-SDcard

Imitate SDcard using FPGAs.

✭ 26

SystemVerilog pascal fpga rtl verilog sdcard sdio

sv-tests

Test suite designed to check compliance with the SystemVerilog standard.

✭ 148

SystemVerilog python javascript CSS HTML Makefile rtl verilog hdl compliance-testing symbiflow

blarney

Haskell library for hardware description

✭ 81

haskell Verilog shell fpga rtl verilog hardware-description

32-Verilog-Mini-Projects

Implementing 32 Verilog Mini Projects. 32 bit adder, Array Multiplier, Barrel Shifter, Binary Divider 16 by 8, Booth Multiplication, CRC Coding, Carry Select and Carry Look Ahead Adder, Carry Skip and Carry Save Adder, Complex Multiplier, Dice Game, FIFO, Fixed Point Adder and Subtractor, Fixed Point Multiplier and Divider, Floating Point IEEE 7…

✭ 66

Verilog python verilog verilog-hdl miniproject verilog-project

ofdm

Chisel Things for OFDM

✭ 23

scala python C++shell Makefile assembly Verilog chip-generator chisel rtl chisel3 firrtl verilog

intfftk

Fully pipelined Integer Scaled / Unscaled Radix-2 Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source language - VHDL / Verilog). GNU GPL 3.0.

✭ 43

VHDL Verilog matlab fpga dsp vhdl verilog fast-fourier-transform xilinx fft vivado altera cooley-tukey-fft digital-signal-processing fast-convolutions radix-2 integer-arithmetic route-optimization

Speech256

An FPGA implementation of a classic 80ies speech synthesizer. Done for the Retro Challenge 2017/10.

✭ 51

Verilog python fpga speech synthesizer verilog hdl retrochallenge

super-miyamoto-sprint

Homebrew game for homebrew FPGA game console

✭ 48

c Makefile C++game fpga verilog risc-v baremetal

docker

Scripts to build and use docker images including GHDL

✭ 27

shell Dockerfile dockerfiles hardware ci simulation vhdl actions verilog synthesis icestorm gtkwave ghdl testbench vunit yosys openocd pnr nextpnr prjtrellis

VGChips

Video Game custom chips reverse-engineered from silicon

✭ 86

Verilog asic fpga reverse-engineering arcade verilog chip hdl silicon cpld repro taito decap

dpll

A collection of phase locked loop (PLL) related projects

✭ 55

Verilog C++matlab Makefile shell fpga gplv3 verilog verilator pll

rapcores

Robotic Application Processor

✭ 14

Verilog c Makefile Nix C++shell fpga robotics verilog cnc motors 3d-printing

verilogAST-cpp

C++17 implementation of an AST for Verilog code generation

✭ 14

C++CMake ast verilog abstract-syntax-tree

FPGA-USB-Device

FPGA-based USB-device controller to implement USB-CDC, USB-HID, etc.

✭ 29

SystemVerilog fpga usb rtl verilog usb-hid usb-uart usb-cdc usb-serial usb-keyboard usb-device usb-device-controller

Deep-DarkFantasy

Global Dark Mode for ALL apps on ANY platforms.

✭ 16

Verilog tcl SystemVerilog Makefile shell javascript fpga zynq dark-theme verilog xilinx vivado verilog-hdl dark-mode zynq-7000 dark-mode-toggle

1bitSDR

Minimal SDR with Lattice MachXO2 FPGA. And a port to Cyclone3 by Steven Groom

✭ 53

VHDL Verilog HTML c SystemVerilog V fpga ham-radio amateur-radio verilog sdr lattice lattice-machxo2

hwt

VHDL/Verilog/SystemC code generator, simulator API written in python/c++

✭ 145

python simulator fpga compiler hls vhdl rtl verilog hcl codegenerator codegen systemc uvm

zx-sizif-512

ZX Spectrum CPLD-based clone for rubber case

✭ 92

KiCad Layout KiCad Schematic SystemVerilog Verilog VHDL assembly zxspectrum pcb z80 verilog zx-spectrum cpld divmmc

getting-started

List of ideas for getting started with TimVideos projects

✭ 50

shell video university fpga usb electronics vhdl mjpeg projects verilog gsoc webcam hdmi usb-devices or1k gsoc-2016 risc-v gsoc-2017 hdmi2usb

sincos

Efficient implementations of the transcendental functions

✭ 22

forth python Verilog c verilog

shapool-core

FPGA core for SHA256d mining targeting Lattice iCE40 devices.

✭ 19

Verilog c python Makefile shell SystemVerilog fpga bitcoin verilog sha256 icestorm ice40 lattice-fpga

math

Useful m-scripts for DSP (CIC, FIR, FFT, Fast convolution, Partial Filters etc.)

✭ 15

matlab fpga math dsp vhdl octave verilog fast-fourier-transform fft digital-signal-processing fir fast-convolutions cic m-scripts

wbi2c

Wishbone controlled I2C controllers

✭ 25

Verilog C++Lex Makefile c shell assembly fpga i2c gplv3 verilog verilator i2c-slave wishbone-bus i2c-master

VerilogLanguageExtension

Verilog Language Extension for Visual Studio

✭ 16

C#Verilog Coq Makefile vsix verilog visual-studio-extension

OpenLane

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, Fault and custom methodology scripts for design exploration and optimization.

✭ 548

Verilog python tcl Dockerfile shell Makefile magic asic rtl verilog vlsi foundry fault yosys klayout caravel netgen system-on-chip openroad openram skywater 130nm soc-design rtl2gds qflow

Icarus Verilog

This repo contains code snippets written in verilog as part of course Computer Architecture of my university curriculum

✭ 28

Verilog verilog computer-architecture verilog-snippets

dblclockfft

A configurable C++ generator of pipelined Verilog FFT cores

✭ 147

C++Verilog Makefile c fpga gplv3 verilog fft verilog-components verilator

ruby-vpi

Ruby interface to IEEE 1364-2005 Verilog VPI

✭ 15

ruby c Verilog simulation verification verilog testing-tools hardware-designs

ProjectOberon2013

Project Oberon (New Edition 2013) Unofficial Mirror

✭ 92

Modula-2 Verilog AMPL shell oberon verilog oberon-system oberon-07

tree-sitter-verilog

Verilog grammar for tree-sitter

✭ 49

c tree-sitter parser verilog hacktoberfest

cocotb-bus

Pre-packaged testbenching tools and reusable bus interfaces for cocotb

✭ 20

python Verilog Makefile interface bus vhdl verilog hdl testbench cocotb

usbcorev

A full-speed device-side USB peripheral core written in Verilog.

✭ 135

Verilog python fpga usb verilog

pcievhost

PCIe (1.0a to 2.0) Virtual host model for verilog

✭ 22

c Verilog Makefile Inno Setup verification verilog virtual modelling cosim pcie pli bfm

FPGA NTP SERVER

A FPGA implementation of the NTP and NTS protocols

✭ 27

Verilog python c Makefile tcl shell SystemVerilog fpga verilog fpga-ntp-server

eddr3

mirror of https://git.elphel.com/Elphel/eddr3

✭ 33

Verilog SystemVerilog python HCL fpga zynq ddr verilog xilinx open-core ddr3 memory-controller

symbolator

HDL symbol generator

✭ 123

python vhdl verilog symbol hdl

R8051

8051 soft CPU core. 700-lines statements for 111 instructions . Fully synthesizable Verilog-2001 core.

✭ 70

Verilog c cpu tiny verilog 8bit

verilog-coding-style

Verilog (SystemVerilog) coding style

✭ 36

coding-standards coding-style verilog

FpOC

FPGA-based Field Oriented Control (FOC) for driving BLDC/PMSM motor.

✭ 138

SystemVerilog Batchfile fpga motor verilog field-oriented-control bldc pmsm foc svpwm

karuta

Karuta HLS Compiler: High level synthesis from prototype based object oriented script language to RTL (Verilog) aiming to be useful for FPGA development.

✭ 89

C++Verilog python fpga verilog iroha

rules verilator

Bazel build rules for Verilator

✭ 14

Starlark bazel bazel-rules verilog verilator

verismith

Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.

✭ 74

haskell python shell verilog fuzzing

cpu11

Revengineered ancient PDP-11 CPUs, originals and clones